Commit bf3753d1 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/backlight: drop DISPLAY_MMIO_BASE() use from backlight registers 



None of the remaining backlight registers that use DISPLAY_MMIO_BASE()
are used on VLV/CHV, which are the only platforms that have non-zero
base. Just drop the DISPLAY_MMIO_BASE() use, reducing the implicit
dev_priv references.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/75ae3f2945912f908df2444d4f0ab97a23b89897.1670405587.git.jani.nikula@intel.com
parent 9e9caa4b

drivers/gpu/drm/i915/display/intel_backlight_regs.h

+3 −3
Original line number Original line Diff line number Diff line
@@ -21,7 +21,7 @@ 
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B)

#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B)





/* Backlight control */

/* Backlight control */

#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */

#define BLC_PWM_CTL2	_MMIO(0x61250) /* 965+ only */

#define   BLM_PWM_ENABLE		(1 << 31)

#define   BLM_PWM_ENABLE		(1 << 31)

#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */

#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */

#define   BLM_PIPE_SELECT		(1 << 29)

#define   BLM_PIPE_SELECT		(1 << 29)
@@ -44,7 +44,7 @@ 
#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)

#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)

#define   BLM_PHASE_IN_INCR_SHIFT	(0)

#define   BLM_PHASE_IN_INCR_SHIFT	(0)

#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)

#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)

#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)

#define BLC_PWM_CTL	_MMIO(0x61254)

/*

/*

 * This is the most significant 15 bits of the number of backlight cycles in a

 * This is the most significant 15 bits of the number of backlight cycles in a

 * complete cycle of the modulated backlight control.

 * complete cycle of the modulated backlight control.
@@ -66,7 +66,7 @@ 
#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)

#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)

#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */

#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */





#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)

#define BLC_HIST_CTL	_MMIO(0x61260)

#define  BLM_HISTOGRAM_ENABLE			(1 << 31)

#define  BLM_HISTOGRAM_ENABLE			(1 << 31)





/* New registers for PCH-split platforms. Safe where new bits show up, the

/* New registers for PCH-split platforms. Safe where new bits show up, the