Commit c4ac5c37 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
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ARM: dts: meson8: add the DDR clock controller 



Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reported-by: default avatarkbuild test robot <lkp@intel.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 630ea310

arch/arm/boot/dts/meson8.dtsi

+11 −2
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Copyright 2014 Carlo Caione <carlo@caione.org>

 */



#include <dt-bindings/clock/meson8-ddr-clkc.h>

#include <dt-bindings/clock/meson8b-clkc.h>

#include <dt-bindings/gpio/meson8-gpio.h>

#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -195,6 +196,14 @@ mmcbus: bus@c8000000 { 
		#size-cells = <1>;

		ranges = <0x0 0xc8000000 0x8000>;



		ddr_clkc: clock-controller@400 {

			compatible = "amlogic,meson8-ddr-clkc";

			reg = <0x400 0x20>;

			clocks = <&xtal>;

			clock-names = "xtal";

			#clock-cells = <1>;

		};



		dmcbus: bus@6000 {

			compatible = "simple-bus";

			reg = <0x6000 0x400>;
@@ -455,8 +464,8 @@ &gpio_intc { 
&hhi {

	clkc: clock-controller {

		compatible = "amlogic,meson8-clkc";

		clocks = <&xtal>;

		clock-names = "xtal";

		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;

		clock-names = "xtal", "ddr_pll";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};