Commit c86dd986 authored by James Clark's avatar James Clark Committed by Mathieu Poirier
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coresight: etm4x: Cleanup TRCRSCTLRn register accesses 



This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-16-james.clark@arm.com


/* Removed extra new lines */
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent 67493ca4

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c

+5 −2
Original line number Diff line number Diff line
@@ -1726,8 +1726,11 @@ static ssize_t res_ctrl_store(struct device *dev, 
	/* For odd idx pair inversal bit is RES0 */

	if (idx % 2 != 0)

		/* PAIRINV, bit[21] */

		val &= ~BIT(21);

	config->res_ctrl[idx] = val & GENMASK(21, 0);

		val &= ~TRCRSCTLRn_PAIRINV;

	config->res_ctrl[idx] = val & (TRCRSCTLRn_PAIRINV |

				       TRCRSCTLRn_INV |

				       TRCRSCTLRn_GROUP_MASK |

				       TRCRSCTLRn_SELECT_MASK);

	spin_unlock(&drvdata->spinlock);

	return size;

}

drivers/hwtracing/coresight/coresight-etm4x.h

+5 −0
Original line number Diff line number Diff line
@@ -223,6 +223,11 @@ 
#define TRCBBCTLR_MODE				BIT(8)

#define TRCBBCTLR_RANGE_MASK			GENMASK(7, 0)



#define TRCRSCTLRn_PAIRINV			BIT(21)

#define TRCRSCTLRn_INV				BIT(20)

#define TRCRSCTLRn_GROUP_MASK			GENMASK(19, 16)

#define TRCRSCTLRn_SELECT_MASK			GENMASK(15, 0)



/*

 * System instructions to access ETM registers.

 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions