Commit ca679c49 authored by Richard Zhu's avatar Richard Zhu Committed by Vinod Koul
Browse files

phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver 



To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
driver.
- Use gpr compatible string to avoid the codes duplications when add
  another platform PCIe PHY support.
- Re-arrange the codes to let it more flexible and easy to expand.
No functional change. Re-arrange the TX tuning, since internal registers
can be wrote through APB interface before assertion of CMN_RST.

Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Tested-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarRichard Leitner <richard.leitner@skidata.com>
Tested-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarAhmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.kernel.org/r/1665625622-20551-4-git-send-email-hongxing.zhu@nxp.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e9e7dca5

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

+66 −40
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/mfd/syscon.h>

#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/phy/phy.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>
@@ -45,6 +46,15 @@ 
#define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)

#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)



enum imx8_pcie_phy_type {

	IMX8MM,

};



struct imx8_pcie_phy_drvdata {

	const	char			*gpr;

	enum	imx8_pcie_phy_type	variant;

};



struct imx8_pcie_phy {

	void __iomem		*base;

	struct clk		*clk;
@@ -55,6 +65,7 @@ struct imx8_pcie_phy { 
	u32			tx_deemph_gen1;

	u32			tx_deemph_gen2;

	bool			clkreq_unused;

	const struct imx8_pcie_phy_drvdata	*drvdata;

};



static int imx8_pcie_phy_power_on(struct phy *phy)
@@ -66,31 +77,17 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
	reset_control_assert(imx8_phy->reset);



	pad_mode = imx8_phy->refclk_pad_mode;

	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,

			   imx8_phy->clkreq_unused ?

			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_AUX_EN,

			   IMX8MM_GPR_PCIE_AUX_EN);

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_POWER_OFF, 0);

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_SSC_EN, 0);



	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_REF_CLK_SEL,

			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?

			   IMX8MM_GPR_PCIE_REF_CLK_EXT :

			   IMX8MM_GPR_PCIE_REF_CLK_PLL);

	usleep_range(100, 200);



	/* Do the PHY common block reset */

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_CMN_RST,

			   IMX8MM_GPR_PCIE_CMN_RST);

	usleep_range(200, 500);

	switch (imx8_phy->drvdata->variant) {

	case IMX8MM:

		/* Tune PHY de-emphasis setting to pass PCIe compliance. */

		if (imx8_phy->tx_deemph_gen1)

			writel(imx8_phy->tx_deemph_gen1,

			       imx8_phy->base + PCIE_PHY_TRSV_REG5);

		if (imx8_phy->tx_deemph_gen2)

			writel(imx8_phy->tx_deemph_gen2,

			       imx8_phy->base + PCIE_PHY_TRSV_REG6);

		break;

	}



	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||

	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -118,15 +115,37 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);

	}



	/* Tune PHY de-emphasis setting to pass PCIe compliance. */

	if (imx8_phy->tx_deemph_gen1)

		writel(imx8_phy->tx_deemph_gen1,

		       imx8_phy->base + PCIE_PHY_TRSV_REG5);

	if (imx8_phy->tx_deemph_gen2)

		writel(imx8_phy->tx_deemph_gen2,

		       imx8_phy->base + PCIE_PHY_TRSV_REG6);

	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,

			   imx8_phy->clkreq_unused ?

			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_AUX_EN,

			   IMX8MM_GPR_PCIE_AUX_EN);

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_POWER_OFF, 0);

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_SSC_EN, 0);



	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_REF_CLK_SEL,

			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?

			   IMX8MM_GPR_PCIE_REF_CLK_EXT :

			   IMX8MM_GPR_PCIE_REF_CLK_PLL);

	usleep_range(100, 200);



	/* Do the PHY common block reset */

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_CMN_RST,

			   IMX8MM_GPR_PCIE_CMN_RST);



	switch (imx8_phy->drvdata->variant) {

	case IMX8MM:

		reset_control_deassert(imx8_phy->reset);

		usleep_range(200, 500);

		break;

	}



	/* Polling to check the phy is ready or not. */

	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
@@ -157,6 +176,17 @@ static const struct phy_ops imx8_pcie_phy_ops = { 
	.owner		= THIS_MODULE,

};



static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {

	.gpr = "fsl,imx8mm-iomuxc-gpr",

	.variant = IMX8MM,

};



static const struct of_device_id imx8_pcie_phy_of_match[] = {

	{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },

	{ },

};

MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);



static int imx8_pcie_phy_probe(struct platform_device *pdev)

{

	struct phy_provider *phy_provider;
@@ -169,6 +199,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev) 
	if (!imx8_phy)

		return -ENOMEM;



	imx8_phy->drvdata = of_device_get_match_data(dev);



	/* get PHY refclk pad mode */

	of_property_read_u32(np, "fsl,refclk-pad-mode",

			     &imx8_phy->refclk_pad_mode);
@@ -194,7 +226,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev) 


	/* Grab GPR config register range */

	imx8_phy->iomuxc_gpr =

		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");

		 syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);

	if (IS_ERR(imx8_phy->iomuxc_gpr)) {

		dev_err(dev, "unable to find iomuxc registers\n");

		return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -222,12 +254,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev) 
	return PTR_ERR_OR_ZERO(phy_provider);

}



static const struct of_device_id imx8_pcie_phy_of_match[] = {

	{.compatible = "fsl,imx8mm-pcie-phy",},

	{ },

};

MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);



static struct platform_driver imx8_pcie_phy_driver = {

	.probe	= imx8_pcie_phy_probe,

	.driver = {