Commit e9e7dca5 authored by Richard Zhu's avatar Richard Zhu Committed by Vinod Koul
Browse files

phy: freescale: imx8m-pcie: Refine register definitions 



No function changes, refine PHY register definitions.
- Keep align with other CMN PHY registers, refine the definitions of
  PHY_CMN_REG75.
- Remove two BIT definitions that are not used at all.

Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Tested-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarRichard Leitner <richard.leitner@skidata.com>
Tested-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/1665625622-20551-3-git-send-email-hongxing.zhu@nxp.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 25caed3d

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

+4 −7
Original line number Diff line number Diff line
@@ -31,12 +31,10 @@ 
#define IMX8MM_PCIE_PHY_CMN_REG065	0x194

#define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))

#define  ANA_AUX_TX_LVL			GENMASK(3, 0)

#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4

#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3

#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4

#define  ANA_PLL_DONE			0x3

#define PCIE_PHY_TRSV_REG5		0x414

#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D

#define PCIE_PHY_TRSV_REG6		0x418

#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF



#define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)

#define IMX8MM_GPR_PCIE_REF_CLK_PLL	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -131,9 +129,8 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
	reset_control_deassert(imx8_phy->reset);



	/* Polling to check the phy is ready or not. */

	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,

				 val, val == PCIE_PHY_CMN_REG75_PLL_DONE,

				 10, 20000);

	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,

				 val, val == ANA_PLL_DONE, 10, 20000);

	return ret;

}