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Unverified Commit ccb1fa21 authored by Jiaxin Yu's avatar Jiaxin Yu Committed by Mark Brown
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ASoC: mediatek: mt6358: add delay after dmic clock on



Most dmics produce a high level when they receive clock. The difference
between power-on and memory record time is about 10ms, but the dmic
needs 50ms to output normal data.

This commit add 100ms delay after SoC output clock so that we can cut
off the pop noise at the beginning.

Signed-off-by: default avatarJiaxin Yu <jiaxin.yu@mediatek.com>
Link: https://lore.kernel.org/r/1564980997-11359-1-git-send-email-jiaxin.yu@mediatek.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent d59170b4
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