Commit cd92fdfc authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/errata' into for-next/core 

* for-next/errata:
  arm64: Add cavium_erratum_23154_cpus missing sentinel
  irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
parents b523d6b8 f90205b9

Documentation/arm64/silicon-errata.rst

+1 −1
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144        |

+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |

| Cavium         | ThunderX GICv3  | #23154,38545    | CAVIUM_ERRATUM_23154        |

+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX GICv3  | #38539          | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+6 −2
Original line number Diff line number Diff line
@@ -891,13 +891,17 @@ config CAVIUM_ERRATUM_23144 
	  If unsure, say Y.



config CAVIUM_ERRATUM_23154

	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"

	bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"

	default y

	help

	  The gicv3 of ThunderX requires a modified version for

	  The ThunderX GICv3 implementation requires a modified version for

	  reading the IAR status to ensure data synchronization

	  (access to icc_iar1_el1 is not sync'ed before and after).



	  It also suffers from erratum 38545 (also present on Marvell's

	  OcteonTX and OcteonTX2), resulting in deactivated interrupts being

	  spuriously presented to the CPU interface.



	  If unsure, say Y.



config CAVIUM_ERRATUM_27456

arch/arm64/include/asm/arch_gicv3.h

+21 −2
Original line number Diff line number Diff line
@@ -53,17 +53,36 @@ static inline u64 gic_read_iar_common(void) 
 * The gicv3 of ThunderX requires a modified version for reading the

 * IAR status to ensure data synchronization (access to icc_iar1_el1

 * is not sync'ed before and after).

 *

 * Erratum 38545

 *

 * When a IAR register read races with a GIC interrupt RELEASE event,

 * GIC-CPU interface could wrongly return a valid INTID to the CPU

 * for an interrupt that is already released(non activated) instead of 0x3ff.

 *

 * To workaround this, return a valid interrupt ID only if there is a change

 * in the active priority list after the IAR read.

 *

 * Common function used for both the workarounds since,

 * 1. On Thunderx 88xx 1.x both erratas are applicable.

 * 2. Having extra nops doesn't add any side effects for Silicons where

 *    erratum 23154 is not applicable.

 */

static inline u64 gic_read_iar_cavium_thunderx(void)

{

	u64 irqstat;

	u64 irqstat, apr;



	apr = read_sysreg_s(SYS_ICC_AP1R0_EL1);

	nops(8);

	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);

	nops(4);

	mb();



	/* Max priority groups implemented is only 32 */

	if (likely(apr != read_sysreg_s(SYS_ICC_AP1R0_EL1)))

		return irqstat;



	return 0x3ff;

}



static inline void gic_write_ctlr(u32 val)

arch/arm64/include/asm/cputype.h

+13 −0
Original line number Diff line number Diff line
@@ -84,6 +84,13 @@ 
#define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2

#define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3

#define CAVIUM_CPU_PART_THUNDERX2	0x0AF

/* OcteonTx2 series */

#define CAVIUM_CPU_PART_OCTX2_98XX	0x0B1

#define CAVIUM_CPU_PART_OCTX2_96XX	0x0B2

#define CAVIUM_CPU_PART_OCTX2_95XX	0x0B3

#define CAVIUM_CPU_PART_OCTX2_95XXN	0x0B4

#define CAVIUM_CPU_PART_OCTX2_95XXMM	0x0B5

#define CAVIUM_CPU_PART_OCTX2_95XXO	0x0B6



#define BRCM_CPU_PART_BRAHMA_B53	0x100

#define BRCM_CPU_PART_VULCAN		0x516
@@ -124,6 +131,12 @@ 
#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)

#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)

#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)

#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)

#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)

#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)

#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)

#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)

#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)

arch/arm64/kernel/cpu_errata.c

+18 −3
Original line number Diff line number Diff line
@@ -214,6 +214,21 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 
};

#endif



#ifdef CONFIG_CAVIUM_ERRATUM_23154

const struct midr_range cavium_erratum_23154_cpus[] = {

	MIDR_ALL_VERSIONS(MIDR_THUNDERX),

	MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX),

	MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX),

	MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX),

	MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX),

	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX),

	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),

	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),

	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),

	{},

};

#endif



#ifdef CONFIG_CAVIUM_ERRATUM_27456

const struct midr_range cavium_erratum_27456_cpus[] = {

	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
@@ -425,10 +440,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_CAVIUM_ERRATUM_23154

	{

	/* Cavium ThunderX, pass 1.x */

		.desc = "Cavium erratum 23154",

		.desc = "Cavium errata 23154 and 38545",

		.capability = ARM64_WORKAROUND_CAVIUM_23154,

		ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus),

	},

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_27456