Unverified Commit d40a2f50 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'riscv-dt-for-v6.4' of... 

Merge tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into soc/dt

RISC-V Devicetrees for v6.4

Microchip:
A "fix" for the system controller's regs on PolarFire SoC, adding a
missing reg property.
The patch had been sitting there for months and I only re-found it
recently, so you can guess how much of a "fix" it actually is. It'll
become needed when the system controller's QSPI gets added in the future,
but at present there's no urgency as the driver can handle both the
current and "fixed" versions.

StarFive:
Basic support for the JH7110 & the associated first-party dev board, the
VisionFive v2 (in two forms). There's a bunch of dt-bindings required
for this too, all of which have had input from the DT folk. There's
enough in this tag to boot to a console w/ an initramfs but little more.
The SoC supports some of the "new" bit manipulation instructions, which
is a good test for the recently added Zbb support in the kernel.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
  riscv: dts: starfive: Add StarFive JH7110 pin function definitions
  riscv: dts: starfive: Add initial StarFive JH7110 device tree
  dt-bindings: riscv: Add SiFive S7 compatible
  dt-bindings: interrupt-controller: Add StarFive JH7110 plic
  dt-bindings: timer: Add StarFive JH7110 clint
  dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
  riscv: dts: microchip: fix the mpfs' mailbox regs
  riscv: dts: microchip: add mpfs specific macb reset support

Link: https://lore.kernel.org/r/20230406-shank-impromptu-3d483bbc249f@spud


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents acda89d6 4cd4beb9

Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Always-On Clock and Reset Generator



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7110-aoncrg



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference or GMAC0 RGMII RX

          - description: STG AXI/AHB

          - description: APB Bus

          - description: GMAC0 GTX



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference or GMAC0 RGMII RX

          - description: STG AXI/AHB or GMAC0 RGMII RX

          - description: APB Bus or STG AXI/AHB

          - description: GMAC0 GTX or APB Bus

          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference

          - description: GMAC0 RGMII RX

          - description: STG AXI/AHB

          - description: APB Bus

          - description: GMAC0 GTX

          - description: RTC Oscillator (32.768 kHz)



  clock-names:

    oneOf:

      - minItems: 5

        items:

          - const: osc

          - enum:

              - gmac0_rmii_refin

              - gmac0_rgmii_rxin

          - const: stg_axiahb

          - const: apb_bus

          - const: gmac0_gtxclk

          - const: rtc_osc



      - minItems: 6

        items:

          - const: osc

          - const: gmac0_rmii_refin

          - const: gmac0_rgmii_rxin

          - const: stg_axiahb

          - const: apb_bus

          - const: gmac0_gtxclk

          - const: rtc_osc



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>



    clock-controller@17000000 {

        compatible = "starfive,jh7110-aoncrg";

        reg = <0x17000000 0x10000>;

        clocks = <&osc>, <&gmac0_rmii_refin>,

                 <&gmac0_rgmii_rxin>,

                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,

                 <&syscrg JH7110_SYSCLK_APB_BUS>,

                 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,

                 <&rtc_osc>;

        clock-names = "osc", "gmac0_rmii_refin",

                      "gmac0_rgmii_rxin", "stg_axiahb",

                      "apb_bus", "gmac0_gtxclk",

                      "rtc_osc";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 System Clock and Reset Generator



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7110-syscrg



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC1 RMII reference or GMAC1 RGMII RX

          - description: External I2S TX bit clock

          - description: External I2S TX left/right channel clock

          - description: External I2S RX bit clock

          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC1 RMII reference

          - description: GMAC1 RGMII RX

          - description: External I2S TX bit clock

          - description: External I2S TX left/right channel clock

          - description: External I2S RX bit clock

          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock



  clock-names:

    oneOf:

      - items:

          - const: osc

          - enum:

              - gmac1_rmii_refin

              - gmac1_rgmii_rxin

          - const: i2stx_bclk_ext

          - const: i2stx_lrck_ext

          - const: i2srx_bclk_ext

          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext



      - items:

          - const: osc

          - const: gmac1_rmii_refin

          - const: gmac1_rgmii_rxin

          - const: i2stx_bclk_ext

          - const: i2stx_lrck_ext

          - const: i2srx_bclk_ext

          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    clock-controller@13020000 {

        compatible = "starfive,jh7110-syscrg";

        reg = <0x13020000 0x10000>;

        clocks = <&osc>, <&gmac1_rmii_refin>,

                 <&gmac1_rgmii_rxin>,

                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

                 <&tdm_ext>, <&mclk_ext>;

        clock-names = "osc", "gmac1_rmii_refin",

                      "gmac1_rgmii_rxin",

                      "i2stx_bclk_ext", "i2stx_lrck_ext",

                      "i2srx_bclk_ext", "i2srx_lrck_ext",

                      "tdm_ext", "mclk_ext";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

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@@ -59,6 +59,7 @@ properties: 
          - enum:

              - sifive,fu540-c000-plic

              - starfive,jh7100-plic

              - starfive,jh7110-plic

              - canaan,k210-plic

          - const: sifive,plic-1.0.0

      - items:

Documentation/devicetree/bindings/riscv/cpus.yaml

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@@ -35,6 +35,7 @@ properties: 
              - sifive,e7

              - sifive,e71

              - sifive,rocket0

              - sifive,s7

              - sifive,u5

              - sifive,u54

              - sifive,u7

Documentation/devicetree/bindings/timer/sifive,clint.yaml

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@@ -31,6 +31,7 @@ properties: 
          - enum:

              - sifive,fu540-c000-clint

              - starfive,jh7100-clint

              - starfive,jh7110-clint

              - canaan,k210-clint

          - const: sifive,clint0

      - items: