Commit dabc114e authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Move to common helper to query soc rev_id 



Replace soc15, nv, soc21 get_rev_id callback with common
helper so we don't need to duplicate code when introduce
new asics.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLikun Gao <Likun.Gao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 65ba96e9

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -1118,7 +1118,7 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 
				 u32 reg_addr, u32 reg_data);

void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,

				   u32 reg_addr, u64 reg_data);



u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);

bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);

bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+12 −0
Original line number Diff line number Diff line
@@ -807,6 +807,18 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 
	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

}



/**

 * amdgpu_device_get_rev_id - query device rev_id

 *

 * @adev: amdgpu_device pointer

 *

 * Return device rev_id

 */

u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)

{

	return adev->nbio.funcs->get_rev_id(adev);

}



/**

 * amdgpu_invalid_rreg - dummy reg read function

 *

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −6
Original line number Diff line number Diff line
@@ -567,11 +567,6 @@ void nv_set_virt_ops(struct amdgpu_device *adev) 
	adev->virt.ops = &xgpu_nv_virt_ops;

}



static uint32_t nv_get_rev_id(struct amdgpu_device *adev)

{

	return adev->nbio.funcs->get_rev_id(adev);

}



static bool nv_need_full_reset(struct amdgpu_device *adev)

{

	return true;
@@ -713,7 +708,7 @@ static int nv_common_early_init(void *handle) 


	adev->asic_funcs = &nv_asic_funcs;



	adev->rev_id = nv_get_rev_id(adev);

	adev->rev_id = amdgpu_device_get_rev_id(adev);

	adev->external_rev_id = 0xff;

	/* TODO: split the GC and PG flags based on the relevant IP version for which

	 * they are relevant.

drivers/gpu/drm/amd/amdgpu/soc15.c

+1 −6
Original line number Diff line number Diff line
@@ -654,11 +654,6 @@ const struct amdgpu_ip_block_version vega10_common_ip_block = 
	.funcs = &soc15_common_ip_funcs,

};



static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)

{

	return adev->nbio.funcs->get_rev_id(adev);

}



static void soc15_reg_base_init(struct amdgpu_device *adev)

{

	/* Set IP register base before any HW register access */
@@ -908,7 +903,7 @@ static int soc15_common_early_init(void *handle) 
	adev->se_cac_rreg = &soc15_se_cac_rreg;

	adev->se_cac_wreg = &soc15_se_cac_wreg;



	adev->rev_id = soc15_get_rev_id(adev);

	adev->rev_id = amdgpu_device_get_rev_id(adev);

	adev->external_rev_id = 0xFF;

	/* TODO: split the GC and PG flags based on the relevant IP version for which

	 * they are relevant.

drivers/gpu/drm/amd/amdgpu/soc21.c

+1 −6
Original line number Diff line number Diff line
@@ -481,11 +481,6 @@ const struct amdgpu_ip_block_version soc21_common_ip_block = 
	.funcs = &soc21_common_ip_funcs,

};



static uint32_t soc21_get_rev_id(struct amdgpu_device *adev)

{

	return adev->nbio.funcs->get_rev_id(adev);

}



static bool soc21_need_full_reset(struct amdgpu_device *adev)

{

	switch (adev->ip_versions[GC_HWIP][0]) {
@@ -626,7 +621,7 @@ static int soc21_common_early_init(void *handle) 


	adev->asic_funcs = &soc21_asic_funcs;



	adev->rev_id = soc21_get_rev_id(adev);

	adev->rev_id = amdgpu_device_get_rev_id(adev);

	adev->external_rev_id = 0xff;

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(11, 0, 0):