Commit dd54ba8b authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: adc: ti-ads7950: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 902c4b24 ("iio: adc: New driver for TI ADS7950 chips")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: default avatarDavid Lechner <david@lechnology.com>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-37-jic23@kernel.org
parent 55afdd05

drivers/iio/adc/ti-ads7950.c

+2 −2
Original line number Diff line number Diff line
@@ -102,11 +102,11 @@ struct ti_ads7950_state { 
	unsigned int		gpio_cmd_settings_bitmask;



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]

							____cacheline_aligned;

		__aligned(IIO_DMA_MINALIGN);

	u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];

	u16 single_tx;

	u16 single_rx;