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Commit e0cffa9a authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Thierry Reding
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ARM: tegra: apalis-tk1: reorder cpu dfll clock properties 



Reorder CPU DFLL clock properties.

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a052d2b6
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