Commit e2da4654 authored by Andrzej Pietrasiewicz's avatar Andrzej Pietrasiewicz Committed by Mauro Carvalho Chehab
Browse files

media: hantro: Support VP9 on the G2 core 



VeriSilicon Hantro G2 core supports VP9 codec.

[hverkuil: add kerneldoc line for HANTRO_MODE_VP9_DEC]

Signed-off-by: default avatarAndrzej Pietrasiewicz <andrzej.p@collabora.com>
Reviewed-by: default avatarBenjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent cb1bbbd4

drivers/staging/media/hantro/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ config VIDEO_HANTRO 
	select VIDEOBUF2_VMALLOC

	select V4L2_MEM2MEM_DEV

	select V4L2_H264

	select V4L2_VP9

	help

	  Support for the Hantro IP based Video Processing Units present on

	  Rockchip and NXP i.MX8M SoCs, which accelerate video and image

drivers/staging/media/hantro/Makefile

+4 −2
Original line number Diff line number Diff line
@@ -10,9 +10,10 @@ hantro-vpu-y += \ 
		hantro_g1.o \

		hantro_g1_h264_dec.o \

		hantro_g1_mpeg2_dec.o \

		hantro_g2_hevc_dec.o \

		hantro_g1_vp8_dec.o \

		hantro_g2.o \

		hantro_g2_hevc_dec.o \

		hantro_g2_vp9_dec.o \

		rockchip_vpu2_hw_jpeg_enc.o \

		rockchip_vpu2_hw_h264_dec.o \

		rockchip_vpu2_hw_mpeg2_dec.o \
@@ -21,7 +22,8 @@ hantro-vpu-y += \ 
		hantro_h264.o \

		hantro_hevc.o \

		hantro_mpeg2.o \

		hantro_vp8.o

		hantro_vp8.o \

		hantro_vp9.o



hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \

		imx8m_vpu_hw.o

drivers/staging/media/hantro/hantro.h

+27 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ struct hantro_postproc_ops; 
#define HANTRO_VP8_DECODER	BIT(17)

#define HANTRO_H264_DECODER	BIT(18)

#define HANTRO_HEVC_DECODER	BIT(19)

#define HANTRO_VP9_DECODER	BIT(20)

#define HANTRO_DECODERS		0xffff0000



/**
@@ -102,6 +103,7 @@ struct hantro_variant { 
 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.

 * @HANTRO_MODE_VP8_DEC: VP8 decoder.

 * @HANTRO_MODE_HEVC_DEC: HEVC decoder.

 * @HANTRO_MODE_VP9_DEC: VP9 decoder.

 */

enum hantro_codec_mode {

	HANTRO_MODE_NONE = -1,
@@ -110,6 +112,7 @@ enum hantro_codec_mode { 
	HANTRO_MODE_MPEG2_DEC,

	HANTRO_MODE_VP8_DEC,

	HANTRO_MODE_HEVC_DEC,

	HANTRO_MODE_VP9_DEC,

};



/*
@@ -223,6 +226,7 @@ struct hantro_dev { 
 * @mpeg2_dec:		MPEG-2-decoding context.

 * @vp8_dec:		VP8-decoding context.

 * @hevc_dec:		HEVC-decoding context.

 * @vp9_dec:		VP9-decoding context.

 */

struct hantro_ctx {

	struct hantro_dev *dev;
@@ -250,6 +254,7 @@ struct hantro_ctx { 
		struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;

		struct hantro_vp8_dec_hw_ctx vp8_dec;

		struct hantro_hevc_dec_hw_ctx hevc_dec;

		struct hantro_vp9_dec_hw_ctx vp9_dec;

	};

};
@@ -299,6 +304,22 @@ struct hantro_postproc_regs { 
	struct hantro_reg display_width;

};



struct hantro_vp9_decoded_buffer_info {

	/* Info needed when the decoded frame serves as a reference frame. */

	unsigned short width;

	unsigned short height;

	u32 bit_depth : 4;

};



struct hantro_decoded_buffer {

	/* Must be the first field in this struct. */

	struct v4l2_m2m_buffer base;



	union {

		struct hantro_vp9_decoded_buffer_info vp9;

	};

};



/* Logging helpers */



/**
@@ -436,6 +457,12 @@ hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb) 
	return vb2_dma_contig_plane_dma_addr(vb, 0);

}



static inline struct hantro_decoded_buffer *

vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)

{

	return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);

}



void hantro_postproc_disable(struct hantro_ctx *ctx);

void hantro_postproc_enable(struct hantro_ctx *ctx);

void hantro_postproc_free(struct hantro_ctx *ctx);

drivers/staging/media/hantro/hantro_drv.c

+17 −1
Original line number Diff line number Diff line
@@ -232,7 +232,7 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 
	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;

	dst_vq->drv_priv = ctx;

	dst_vq->ops = &hantro_queue_ops;

	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);

	dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer);

	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;

	dst_vq->lock = &ctx->dev->vpu_mutex;

	dst_vq->dev = ctx->dev->v4l2_dev.dev;
@@ -263,6 +263,12 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) 
		if (sps->bit_depth_luma_minus8 != 0)

			/* Only 8-bit is supported */

			return -EINVAL;

	} else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {

		const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;



		/* We only support profile 0 */

		if (dec_params->profile != 0)

			return -EINVAL;

	}

	return 0;

}
@@ -461,6 +467,16 @@ static const struct hantro_ctrl controls[] = { 
			.step = 1,

			.ops = &hantro_hevc_ctrl_ops,

		},

	}, {

		.codec = HANTRO_VP9_DECODER,

		.cfg = {

			.id = V4L2_CID_STATELESS_VP9_FRAME,

		},

	}, {

		.codec = HANTRO_VP9_DECODER,

		.cfg = {

			.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,

		},

	},

};

drivers/staging/media/hantro/hantro_g2_regs.h

+97 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#define G2_REG_INTERRUPT_DEC_E		BIT(0)



#define HEVC_DEC_MODE			0xc

#define VP9_DEC_MODE			0xd



#define BUS_WIDTH_32			0

#define BUS_WIDTH_64			1
@@ -49,6 +50,7 @@ 
#define g2_pic_height_in_cbs	G2_DEC_REG(4, 6,  0x1fff)

#define g2_num_ref_frames	G2_DEC_REG(4, 0,  0x1f)



#define g2_start_bit		G2_DEC_REG(5, 25, 0x7f)

#define g2_scaling_list_e	G2_DEC_REG(5, 24, 0x1)

#define g2_cb_qp_offset		G2_DEC_REG(5, 19, 0x1f)

#define g2_cr_qp_offset		G2_DEC_REG(5, 14, 0x1f)
@@ -84,6 +86,7 @@ 
#define g2_bit_depth_y_minus8	G2_DEC_REG(8, 6,  0x3)

#define g2_bit_depth_c_minus8	G2_DEC_REG(8, 4,  0x3)

#define g2_output_8_bits	G2_DEC_REG(8, 3,  0x1)

#define g2_output_format	G2_DEC_REG(8, 0,  0x7)



#define g2_refidx1_active	G2_DEC_REG(9, 19, 0x1f)

#define g2_refidx0_active	G2_DEC_REG(9, 14, 0x1f)
@@ -96,6 +99,14 @@ 
#define g2_tile_e		G2_DEC_REG(10, 1,  0x1)

#define g2_entropy_sync_e	G2_DEC_REG(10, 0,  0x1)



#define vp9_transform_mode	G2_DEC_REG(11, 27, 0x7)

#define vp9_filt_sharpness	G2_DEC_REG(11, 21, 0x7)

#define vp9_mcomp_filt_type	G2_DEC_REG(11,  8, 0x7)

#define vp9_high_prec_mv_e	G2_DEC_REG(11,  7, 0x1)

#define vp9_comp_pred_mode	G2_DEC_REG(11,  4, 0x3)

#define vp9_gref_sign_bias	G2_DEC_REG(11,  2, 0x1)

#define vp9_aref_sign_bias	G2_DEC_REG(11,  0, 0x1)



#define g2_refer_lterm_e	G2_DEC_REG(12, 16, 0xffff)

#define g2_min_cb_size		G2_DEC_REG(12, 13, 0x7)

#define g2_max_cb_size		G2_DEC_REG(12, 10, 0x7)
@@ -154,6 +165,50 @@ 
#define g2_partial_ctb_y	G2_DEC_REG(20, 30, 0x1)

#define g2_pic_width_4x4	G2_DEC_REG(20, 16, 0xfff)

#define g2_pic_height_4x4	G2_DEC_REG(20, 0,  0xfff)



#define vp9_qp_delta_y_dc	G2_DEC_REG(13, 23, 0x3f)

#define vp9_qp_delta_ch_dc	G2_DEC_REG(13, 17, 0x3f)

#define vp9_qp_delta_ch_ac	G2_DEC_REG(13, 11, 0x3f)

#define vp9_last_sign_bias	G2_DEC_REG(13, 10, 0x1)

#define vp9_lossless_e		G2_DEC_REG(13,  9, 0x1)

#define vp9_comp_pred_var_ref1	G2_DEC_REG(13,  7, 0x3)

#define vp9_comp_pred_var_ref0	G2_DEC_REG(13,  5, 0x3)

#define vp9_comp_pred_fixed_ref	G2_DEC_REG(13,  3, 0x3)

#define vp9_segment_temp_upd_e	G2_DEC_REG(13,  2, 0x1)

#define vp9_segment_upd_e	G2_DEC_REG(13,  1, 0x1)

#define vp9_segment_e		G2_DEC_REG(13,  0, 0x1)



#define vp9_filt_level		G2_DEC_REG(14, 18, 0x3f)

#define vp9_refpic_seg0		G2_DEC_REG(14, 15, 0x7)

#define vp9_skip_seg0		G2_DEC_REG(14, 14, 0x1)

#define vp9_filt_level_seg0	G2_DEC_REG(14,  8, 0x3f)

#define vp9_quant_seg0		G2_DEC_REG(14,  0, 0xff)



#define vp9_refpic_seg1		G2_DEC_REG(15, 15, 0x7)

#define vp9_skip_seg1		G2_DEC_REG(15, 14, 0x1)

#define vp9_filt_level_seg1	G2_DEC_REG(15,  8, 0x3f)

#define vp9_quant_seg1		G2_DEC_REG(15,  0, 0xff)



#define vp9_refpic_seg2		G2_DEC_REG(16, 15, 0x7)

#define vp9_skip_seg2		G2_DEC_REG(16, 14, 0x1)

#define vp9_filt_level_seg2	G2_DEC_REG(16,  8, 0x3f)

#define vp9_quant_seg2		G2_DEC_REG(16,  0, 0xff)



#define vp9_refpic_seg3		G2_DEC_REG(17, 15, 0x7)

#define vp9_skip_seg3		G2_DEC_REG(17, 14, 0x1)

#define vp9_filt_level_seg3	G2_DEC_REG(17,  8, 0x3f)

#define vp9_quant_seg3		G2_DEC_REG(17,  0, 0xff)



#define vp9_refpic_seg4		G2_DEC_REG(18, 15, 0x7)

#define vp9_skip_seg4		G2_DEC_REG(18, 14, 0x1)

#define vp9_filt_level_seg4	G2_DEC_REG(18,  8, 0x3f)

#define vp9_quant_seg4		G2_DEC_REG(18,  0, 0xff)



#define vp9_refpic_seg5		G2_DEC_REG(19, 15, 0x7)

#define vp9_skip_seg5		G2_DEC_REG(19, 14, 0x1)

#define vp9_filt_level_seg5	G2_DEC_REG(19,  8, 0x3f)

#define vp9_quant_seg5		G2_DEC_REG(19,  0, 0xff)



#define hevc_cur_poc_00		G2_DEC_REG(46, 24, 0xff)

#define hevc_cur_poc_01		G2_DEC_REG(46, 16, 0xff)

#define hevc_cur_poc_02		G2_DEC_REG(46, 8,  0xff)
@@ -174,6 +229,44 @@ 
#define hevc_cur_poc_14		G2_DEC_REG(49, 8,  0xff)

#define hevc_cur_poc_15		G2_DEC_REG(49, 0,  0xff)



#define vp9_refpic_seg6		G2_DEC_REG(31, 15, 0x7)

#define vp9_skip_seg6		G2_DEC_REG(31, 14, 0x1)

#define vp9_filt_level_seg6	G2_DEC_REG(31,  8, 0x3f)

#define vp9_quant_seg6		G2_DEC_REG(31,  0, 0xff)



#define vp9_refpic_seg7		G2_DEC_REG(32, 15, 0x7)

#define vp9_skip_seg7		G2_DEC_REG(32, 14, 0x1)

#define vp9_filt_level_seg7	G2_DEC_REG(32,  8, 0x3f)

#define vp9_quant_seg7		G2_DEC_REG(32,  0, 0xff)



#define vp9_lref_width		G2_DEC_REG(33, 16, 0xffff)

#define vp9_lref_height		G2_DEC_REG(33,  0, 0xffff)



#define vp9_gref_width		G2_DEC_REG(34, 16, 0xffff)

#define vp9_gref_height		G2_DEC_REG(34,  0, 0xffff)



#define vp9_aref_width		G2_DEC_REG(35, 16, 0xffff)

#define vp9_aref_height		G2_DEC_REG(35,  0, 0xffff)



#define vp9_lref_hor_scale	G2_DEC_REG(36, 16, 0xffff)

#define vp9_lref_ver_scale	G2_DEC_REG(36,  0, 0xffff)



#define vp9_gref_hor_scale	G2_DEC_REG(37, 16, 0xffff)

#define vp9_gref_ver_scale	G2_DEC_REG(37,  0, 0xffff)



#define vp9_aref_hor_scale	G2_DEC_REG(38, 16, 0xffff)

#define vp9_aref_ver_scale	G2_DEC_REG(38,  0, 0xffff)



#define vp9_filt_ref_adj_0	G2_DEC_REG(46, 24, 0x7f)

#define vp9_filt_ref_adj_1	G2_DEC_REG(46, 16, 0x7f)

#define vp9_filt_ref_adj_2	G2_DEC_REG(46,  8, 0x7f)

#define vp9_filt_ref_adj_3	G2_DEC_REG(46,  0, 0x7f)



#define vp9_filt_mb_adj_0	G2_DEC_REG(47, 24, 0x7f)

#define vp9_filt_mb_adj_1	G2_DEC_REG(47, 16, 0x7f)

#define vp9_filt_mb_adj_2	G2_DEC_REG(47,  8, 0x7f)

#define vp9_filt_mb_adj_3	G2_DEC_REG(47,  0, 0x7f)



#define g2_apf_threshold	G2_DEC_REG(55, 0, 0xffff)



#define g2_clk_gate_e		G2_DEC_REG(58, 16, 0x1)
@@ -186,6 +279,8 @@ 


#define G2_OUT_LUMA_ADDR		(G2_SWREG(65))

#define G2_REF_LUMA_ADDR(i)		(G2_SWREG(67)  + ((i) * 0x8))

#define G2_VP9_SEGMENT_WRITE_ADDR	(G2_SWREG(79))

#define G2_VP9_SEGMENT_READ_ADDR	(G2_SWREG(81))

#define G2_OUT_CHROMA_ADDR		(G2_SWREG(99))

#define G2_REF_CHROMA_ADDR(i)		(G2_SWREG(101) + ((i) * 0x8))

#define G2_OUT_MV_ADDR			(G2_SWREG(133))
@@ -193,6 +288,8 @@ 
#define G2_TILE_SIZES_ADDR		(G2_SWREG(167))

#define G2_STREAM_ADDR			(G2_SWREG(169))

#define G2_HEVC_SCALING_LIST_ADDR	(G2_SWREG(171))

#define G2_VP9_CTX_COUNT_ADDR		(G2_SWREG(171))

#define G2_VP9_PROBS_ADDR		(G2_SWREG(173))

#define G2_RS_OUT_LUMA_ADDR		(G2_SWREG(175))

#define G2_RS_OUT_CHROMA_ADDR		(G2_SWREG(177))

#define G2_TILE_FILTER_ADDR		(G2_SWREG(179))