Commit e550ad0e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: fix DSC 1.2 block lengths 



All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.

Fixes: 0d1b10c6 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Reported-by: default avatarRyan McCann <quic_rmccann@quicinc.com>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/550998/
Link: https://lore.kernel.org/r/20230802183655.4188640-1-dmitry.baryshkov@linaro.org
parent 42d0d253

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

+4 −4
Original line number Diff line number Diff line
@@ -283,22 +283,22 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { 
static const struct dpu_dsc_cfg sm8350_dsc[] = {

	{

		.name = "dce_0_0", .id = DSC_0,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_0_1", .id = DSC_1,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_1,

	}, {

		.name = "dce_1_0", .id = DSC_2,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_1_1", .id = DSC_3,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_1,

	},

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

+1 −1
Original line number Diff line number Diff line
@@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { 
static const struct dpu_dsc_cfg sc7280_dsc[] = {

	{

		.name = "dce_0_0", .id = DSC_0,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_0,

	},

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

+6 −6
Original line number Diff line number Diff line
@@ -286,32 +286,32 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { 
static const struct dpu_dsc_cfg sc8280xp_dsc[] = {

	{

		.name = "dce_0_0", .id = DSC_0,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_0_1", .id = DSC_1,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_1,

	}, {

		.name = "dce_1_0", .id = DSC_2,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_1_1", .id = DSC_3,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_1,

	}, {

		.name = "dce_2_0", .id = DSC_4,

		.base = 0x82000, .len = 0x29c,

		.base = 0x82000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_2_1", .id = DSC_5,

		.base = 0x82000, .len = 0x29c,

		.base = 0x82000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_1,

	},

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

+4 −4
Original line number Diff line number Diff line
@@ -305,22 +305,22 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 
static const struct dpu_dsc_cfg sm8450_dsc[] = {

	{

		.name = "dce_0_0", .id = DSC_0,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_0_1", .id = DSC_1,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_1,

	}, {

		.name = "dce_1_0", .id = DSC_2,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_1_1", .id = DSC_3,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_1,

	},

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

+4 −4
Original line number Diff line number Diff line
@@ -320,22 +320,22 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 
static const struct dpu_dsc_cfg sm8550_dsc[] = {

	{

		.name = "dce_0_0", .id = DSC_0,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_0_1", .id = DSC_1,

		.base = 0x80000, .len = 0x29c,

		.base = 0x80000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2),

		.sblk = &dsc_sblk_1,

	}, {

		.name = "dce_1_0", .id = DSC_2,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_0,

	}, {

		.name = "dce_1_1", .id = DSC_3,

		.base = 0x81000, .len = 0x29c,

		.base = 0x81000, .len = 0x4,

		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &dsc_sblk_1,

	},