Commit ec255e1c authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields 



Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 422 bytes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
parent be525de9

drivers/pinctrl/renesas/pfc-r8a77995.c

+22 −85
Original line number Diff line number Diff line
@@ -2486,30 +2486,10 @@ static const struct sh_pfc_function pinmux_functions[] = { 
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

#define F_(x, y)	FN_##y

#define FM(x)		FN_##x

	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,

			     GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP0_31_9 RESERVED */

		GP_0_8_FN,	GPSR0_8,

		GP_0_7_FN,	GPSR0_7,

		GP_0_6_FN,	GPSR0_6,
@@ -2588,29 +2568,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_1_FN,	GPSR2_1,

		GP_2_0_FN,	GPSR2_0, ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,

			     GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP3_31_10 RESERVED */

		GP_3_9_FN,	GPSR3_9,

		GP_3_8_FN,	GPSR3_8,

		GP_3_7_FN,	GPSR3_7,
@@ -2656,18 +2617,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_4_1_FN,	GPSR4_1,

		GP_4_0_FN,	GPSR4_0, ))

	},

	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,

			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP5_31_21 RESERVED */

		GP_5_20_FN,	GPSR5_20,

		GP_5_19_FN,	GPSR5_19,

		GP_5_18_FN,	GPSR5_18,
@@ -2690,25 +2644,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_5_1_FN,	GPSR5_1,

		GP_5_0_FN,	GPSR5_0, ))

	},

	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,

			     GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1),

			     GROUP(

		/* GP6_31_14 RESERVED */

		GP_6_13_FN,	GPSR6_13,

		GP_6_12_FN,	GPSR6_12,

		GP_6_11_FN,	GPSR6_11,
@@ -2859,13 +2799,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		IP12_7_4

		IP12_3_0 ))

	},

	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(

		/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP13_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	{ PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,

			     GROUP(-24, 4, 4),

			     GROUP(

		/* IP13_31_8 RESERVED */

		IP13_7_4

		IP13_3_0 ))

	},