Commit ed4fa8c6 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros 



To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/545378/
Link: https://lore.kernel.org/r/20230704022136.130522-18-dmitry.baryshkov@linaro.org
parent 36e2ad1d

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

+40 −12
Original line number Diff line number Diff line
@@ -241,18 +241,46 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = { 
};



static const struct dpu_intf_cfg msm8998_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 21,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 21,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x6b000, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 21,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_3", .id = INTF_3,

		.base = 0x6b800, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_HDMI,

		.prog_fetch_lines_worst_case = 21,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

		.intr_tear_rd_ptr = -1,

	},

};



static const struct dpu_perf_cfg msm8998_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

+41 −12
Original line number Diff line number Diff line
@@ -257,18 +257,47 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = { 
};



static const struct dpu_intf_cfg sdm845_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x6b000, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_3", .id = INTF_3,

		.base = 0x6b800, .len = 0x280,

		.features = INTF_SDM845_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

		.intr_tear_rd_ptr = -1,

	},

};



static const struct dpu_perf_cfg sdm845_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+41 −14
Original line number Diff line number Diff line
@@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = { 
};



static const struct dpu_intf_cfg sm8150_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x2bc,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x6b000, .len = 0x2bc,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),

	}, {

		.name = "intf_3", .id = INTF_3,

		.base = 0x6b800, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

		.intr_tear_rd_ptr = -1,

	},

};



static const struct dpu_perf_cfg sm8150_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+62 −20
Original line number Diff line number Diff line
@@ -313,27 +313,69 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = { 
};



static const struct dpu_intf_cfg sc8180x_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x2bc,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x6b000, .len = 0x2bc,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),

	},

	/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

	INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),

	INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),

	{

		.name = "intf_3", .id = INTF_3,

		.base = 0x6b800, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = 999,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_4", .id = INTF_4,

		.base = 0x6c000, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_5", .id = INTF_5,

		.base = 0x6c800, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_2,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),

		.intr_tear_rd_ptr = -1,

	},

};



static const struct dpu_perf_cfg sc8180x_perf_data = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+41 −14
Original line number Diff line number Diff line
@@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = { 
};



static const struct dpu_intf_cfg sm8250_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x2c0,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x6b000, .len = 0x2c0,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),

	}, {

		.name = "intf_3", .id = INTF_3,

		.base = 0x6b800, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

		.intr_tear_rd_ptr = -1,

	},

};



static const struct dpu_wb_cfg sm8250_wb[] = {