Loading Documentation/powerpc/dts-bindings/fsl/dma.txt +17 −17 Original line number Diff line number Diff line Loading @@ -35,30 +35,30 @@ Example: #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; reg = <82a8 4>; ranges = <0 8100 1a4>; reg = <0x82a8 4>; ranges = <0 0x8100 0x1a4>; interrupt-parent = <&ipic>; interrupts = <47 8>; interrupts = <71 8>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <0>; reg = <0 80>; reg = <0 0x80>; }; dma-channel@80 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <1>; reg = <80 80>; reg = <0x80 0x80>; }; dma-channel@100 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <2>; reg = <100 80>; reg = <0x100 0x80>; }; dma-channel@180 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <3>; reg = <180 80>; reg = <0x180 0x80>; }; }; Loading Loading @@ -93,36 +93,36 @@ Example: #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; reg = <21300 4>; ranges = <0 21100 200>; reg = <0x21300 4>; ranges = <0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <0 80>; reg = <0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <14 2>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <80 80>; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <15 2>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <100 80>; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <16 2>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <180 80>; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <17 2>; interrupts = <23 2>; }; }; Loading Documentation/powerpc/dts-bindings/fsl/esdhc.txt 0 → 100644 +24 −0 Original line number Diff line number Diff line * Freescale Enhanced Secure Digital Host Controller (eSDHC) The Enhanced Secure Digital Host Controller provides an interface for MMC, SD, and SDIO types of memory cards. Required properties: - compatible : should be "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors. "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors. - reg : should contain eSDHC registers location and length. - interrupts : should contain eSDHC interrupt. - interrupt-parent : interrupt source phandle. - clock-frequency : specifies eSDHC base clock frequency. Example: sdhci@2e000 { compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; /* Filled in by U-Boot */ clock-frequency = <0>; }; arch/powerpc/Kconfig +18 −1 Original line number Diff line number Diff line Loading @@ -594,6 +594,7 @@ config FSL_SOC config FSL_PCI bool select PPC_INDIRECT_PCI select PCI_QUIRKS config 4xx_SOC bool Loading Loading @@ -730,6 +731,22 @@ config LOWMEM_SIZE hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL default "0x30000000" config LOWMEM_CAM_NUM_BOOL bool "Set number of CAMs to use to map low memory" depends on ADVANCED_OPTIONS && FSL_BOOKE help This option allows you to set the maximum number of CAM slots that will be used to map low memory. There are a limited number of slots available and even more limited number that will fit in the L1 MMU. However, using more entries will allow mapping more low memory. This can be useful in optimizing the layout of kernel virtual memory. Say N here unless you know what you are doing. config LOWMEM_CAM_NUM int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL default 3 config RELOCATABLE bool "Build a relocatable kernel (EXPERIMENTAL)" depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE Loading Loading @@ -794,7 +811,7 @@ config PHYSICAL_START config PHYSICAL_ALIGN hex default "0x10000000" if FSL_BOOKE default "0x04000000" if FSL_BOOKE help This value puts the alignment restrictions on physical address where kernel is loaded and run from. Kernel is compiled for an Loading arch/powerpc/boot/dts/gef_sbc310.dts 0 → 100644 +364 −0 Original line number Diff line number Diff line /* * GE Fanuc SBC310 Device Tree Source * * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * Based on: SBS CM6 Device Tree Source * Copyright 2007 SBS Technologies GmbH & Co. KG * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) * Copyright 2006 Freescale Semiconductor Inc. */ /* * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts */ /dts-v1/; / { model = "GEF_SBC310"; compatible = "gef,sbc310"; #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8641@0 { device_type = "cpu"; reg = <0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot }; PowerPC,8641@1 { device_type = "cpu"; reg = <1>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot }; }; memory { device_type = "memory"; reg = <0x0 0x40000000>; // set by uboot }; localbus@fef05000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8641-localbus", "simple-bus"; reg = <0xfef05000 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 1 0 0xe0000000 0x08000000 // Paged Flash 0 2 0 0xe8000000 0x08000000 // Paged Flash 1 3 0 0xfc100000 0x00020000 // NVRAM 4 0 0xfc000000 0x00010000>; // FPGA /* flash@0,0 is a mirror of part of the memory in flash@1,0 flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x01000000>; bank-width = <2>; device-width = <2>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "firmware"; reg = <0x00000000 0x01000000>; read-only; }; }; */ flash@1,0 { compatible = "cfi-flash"; reg = <1 0 0x8000000>; bank-width = <2>; device-width = <2>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "user"; reg = <0x00000000 0x07800000>; }; partition@7800000 { label = "firmware"; reg = <0x07800000 0x00800000>; read-only; }; }; fpga@4,0 { compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; }; wdt@4,2000 { #interrupt-cells = <2>; device_type = "watchdog"; compatible = "gef,fpga-wdt"; reg = <0x4 0x2000 0x8>; interrupts = <0x1a 0x4>; interrupt-parent = <&gef_pic>; }; /* wdt@4,2010 { #interrupt-cells = <2>; device_type = "watchdog"; compatible = "gef,fpga-wdt"; reg = <0x4 0x2010 0x8>; interrupts = <0x1b 0x4>; interrupt-parent = <&gef_pic>; }; */ gef_pic: pic@4,4000 { #interrupt-cells = <1>; interrupt-controller; compatible = "gef,fpga-pic"; reg = <0x4 0x4000 0x20>; interrupts = <0x8 0x9>; interrupt-parent = <&mpic>; }; gef_gpio: gpio@4,8000 { #gpio-cells = <2>; compatible = "gef,sbc310-gpio"; reg = <0x4 0x8000 0x24>; gpio-controller; }; }; soc@fef00000 { #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <0x2b 0x2>; interrupt-parent = <&mpic>; dfsrr; rtc@51 { compatible = "epson,rx8581"; reg = <0x00000051>; }; }; i2c2: i2c@3100 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3100 0x100>; interrupts = <0x2b 0x2>; interrupt-parent = <&mpic>; dfsrr; hwmon@48 { compatible = "national,lm92"; reg = <0x48>; }; hwmon@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; eti@6b { compatible = "dallas,ds1682"; reg = <0x6b>; }; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; mdio@24520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&gef_pic>; interrupts = <0x9 0x4>; reg = <1>; }; phy2: ethernet-phy@2 { interrupt-parent = <&gef_pic>; interrupts = <0x8 0x4>; reg = <3>; }; }; enet0: ethernet@24000 { device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; phy-connection-type = "gmii"; }; enet1: ethernet@26000 { device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>; interrupt-parent = <&mpic>; phy-handle = <&phy2>; phy-connection-type = "gmii"; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <0x2a 0x2>; interrupt-parent = <&mpic>; }; serial1: serial@4600 { cell-index = <1>; device_type = "serial"; compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <0x1c 0x2>; interrupt-parent = <&mpic>; }; mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; }; global-utilities@e0000 { compatible = "fsl,mpc8641-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; }; pci0: pcie@fef08000 { compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0xfef08000 0x1000>; bus-range = <0x0 0xff>; ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <0x18 0x2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2 >; pcie@0 { reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000 0x0 0x40000000 0x01000000 0x0 0x00000000 0x01000000 0x0 0x00000000 0x0 0x00400000>; }; }; }; arch/powerpc/boot/dts/mpc8315erdb.dts +64 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,8 @@ aliases { serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; }; cpus { Loading Loading @@ -349,4 +351,66 @@ pci0: pci@e0008500 { compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; pci1: pcie@e0009000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; reg = <0xe0009000 0x00001000>; ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; bus-range = <0 255>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0 0 0 1 &ipic 1 8 0 0 0 2 &ipic 1 8 0 0 0 3 &ipic 1 8 0 0 0 4 &ipic 1 8>; clock-frequency = <0>; pcie@0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; reg = <0 0 0 0 0>; ranges = <0x02000000 0 0xa0000000 0x02000000 0 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00800000>; }; }; pci2: pcie@e000a000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; reg = <0xe000a000 0x00001000>; ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; bus-range = <0 255>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0 0 0 1 &ipic 2 8 0 0 0 2 &ipic 2 8 0 0 0 3 &ipic 2 8 0 0 0 4 &ipic 2 8>; clock-frequency = <0>; pcie@0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; reg = <0 0 0 0 0>; ranges = <0x02000000 0 0xc0000000 0x02000000 0 0xc0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00800000>; }; }; }; Loading
Documentation/powerpc/dts-bindings/fsl/dma.txt +17 −17 Original line number Diff line number Diff line Loading @@ -35,30 +35,30 @@ Example: #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; reg = <82a8 4>; ranges = <0 8100 1a4>; reg = <0x82a8 4>; ranges = <0 0x8100 0x1a4>; interrupt-parent = <&ipic>; interrupts = <47 8>; interrupts = <71 8>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <0>; reg = <0 80>; reg = <0 0x80>; }; dma-channel@80 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <1>; reg = <80 80>; reg = <0x80 0x80>; }; dma-channel@100 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <2>; reg = <100 80>; reg = <0x100 0x80>; }; dma-channel@180 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <3>; reg = <180 80>; reg = <0x180 0x80>; }; }; Loading Loading @@ -93,36 +93,36 @@ Example: #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; reg = <21300 4>; ranges = <0 21100 200>; reg = <0x21300 4>; ranges = <0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <0 80>; reg = <0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <14 2>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <80 80>; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <15 2>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <100 80>; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <16 2>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; reg = <180 80>; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <17 2>; interrupts = <23 2>; }; }; Loading
Documentation/powerpc/dts-bindings/fsl/esdhc.txt 0 → 100644 +24 −0 Original line number Diff line number Diff line * Freescale Enhanced Secure Digital Host Controller (eSDHC) The Enhanced Secure Digital Host Controller provides an interface for MMC, SD, and SDIO types of memory cards. Required properties: - compatible : should be "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors. "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors. - reg : should contain eSDHC registers location and length. - interrupts : should contain eSDHC interrupt. - interrupt-parent : interrupt source phandle. - clock-frequency : specifies eSDHC base clock frequency. Example: sdhci@2e000 { compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; /* Filled in by U-Boot */ clock-frequency = <0>; };
arch/powerpc/Kconfig +18 −1 Original line number Diff line number Diff line Loading @@ -594,6 +594,7 @@ config FSL_SOC config FSL_PCI bool select PPC_INDIRECT_PCI select PCI_QUIRKS config 4xx_SOC bool Loading Loading @@ -730,6 +731,22 @@ config LOWMEM_SIZE hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL default "0x30000000" config LOWMEM_CAM_NUM_BOOL bool "Set number of CAMs to use to map low memory" depends on ADVANCED_OPTIONS && FSL_BOOKE help This option allows you to set the maximum number of CAM slots that will be used to map low memory. There are a limited number of slots available and even more limited number that will fit in the L1 MMU. However, using more entries will allow mapping more low memory. This can be useful in optimizing the layout of kernel virtual memory. Say N here unless you know what you are doing. config LOWMEM_CAM_NUM int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL default 3 config RELOCATABLE bool "Build a relocatable kernel (EXPERIMENTAL)" depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE Loading Loading @@ -794,7 +811,7 @@ config PHYSICAL_START config PHYSICAL_ALIGN hex default "0x10000000" if FSL_BOOKE default "0x04000000" if FSL_BOOKE help This value puts the alignment restrictions on physical address where kernel is loaded and run from. Kernel is compiled for an Loading
arch/powerpc/boot/dts/gef_sbc310.dts 0 → 100644 +364 −0 Original line number Diff line number Diff line /* * GE Fanuc SBC310 Device Tree Source * * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * Based on: SBS CM6 Device Tree Source * Copyright 2007 SBS Technologies GmbH & Co. KG * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) * Copyright 2006 Freescale Semiconductor Inc. */ /* * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts */ /dts-v1/; / { model = "GEF_SBC310"; compatible = "gef,sbc310"; #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8641@0 { device_type = "cpu"; reg = <0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot }; PowerPC,8641@1 { device_type = "cpu"; reg = <1>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot }; }; memory { device_type = "memory"; reg = <0x0 0x40000000>; // set by uboot }; localbus@fef05000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8641-localbus", "simple-bus"; reg = <0xfef05000 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 1 0 0xe0000000 0x08000000 // Paged Flash 0 2 0 0xe8000000 0x08000000 // Paged Flash 1 3 0 0xfc100000 0x00020000 // NVRAM 4 0 0xfc000000 0x00010000>; // FPGA /* flash@0,0 is a mirror of part of the memory in flash@1,0 flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x01000000>; bank-width = <2>; device-width = <2>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "firmware"; reg = <0x00000000 0x01000000>; read-only; }; }; */ flash@1,0 { compatible = "cfi-flash"; reg = <1 0 0x8000000>; bank-width = <2>; device-width = <2>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "user"; reg = <0x00000000 0x07800000>; }; partition@7800000 { label = "firmware"; reg = <0x07800000 0x00800000>; read-only; }; }; fpga@4,0 { compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; }; wdt@4,2000 { #interrupt-cells = <2>; device_type = "watchdog"; compatible = "gef,fpga-wdt"; reg = <0x4 0x2000 0x8>; interrupts = <0x1a 0x4>; interrupt-parent = <&gef_pic>; }; /* wdt@4,2010 { #interrupt-cells = <2>; device_type = "watchdog"; compatible = "gef,fpga-wdt"; reg = <0x4 0x2010 0x8>; interrupts = <0x1b 0x4>; interrupt-parent = <&gef_pic>; }; */ gef_pic: pic@4,4000 { #interrupt-cells = <1>; interrupt-controller; compatible = "gef,fpga-pic"; reg = <0x4 0x4000 0x20>; interrupts = <0x8 0x9>; interrupt-parent = <&mpic>; }; gef_gpio: gpio@4,8000 { #gpio-cells = <2>; compatible = "gef,sbc310-gpio"; reg = <0x4 0x8000 0x24>; gpio-controller; }; }; soc@fef00000 { #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <0x2b 0x2>; interrupt-parent = <&mpic>; dfsrr; rtc@51 { compatible = "epson,rx8581"; reg = <0x00000051>; }; }; i2c2: i2c@3100 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3100 0x100>; interrupts = <0x2b 0x2>; interrupt-parent = <&mpic>; dfsrr; hwmon@48 { compatible = "national,lm92"; reg = <0x48>; }; hwmon@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; eti@6b { compatible = "dallas,ds1682"; reg = <0x6b>; }; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; mdio@24520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&gef_pic>; interrupts = <0x9 0x4>; reg = <1>; }; phy2: ethernet-phy@2 { interrupt-parent = <&gef_pic>; interrupts = <0x8 0x4>; reg = <3>; }; }; enet0: ethernet@24000 { device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; phy-connection-type = "gmii"; }; enet1: ethernet@26000 { device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>; interrupt-parent = <&mpic>; phy-handle = <&phy2>; phy-connection-type = "gmii"; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <0x2a 0x2>; interrupt-parent = <&mpic>; }; serial1: serial@4600 { cell-index = <1>; device_type = "serial"; compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <0x1c 0x2>; interrupt-parent = <&mpic>; }; mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; }; global-utilities@e0000 { compatible = "fsl,mpc8641-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; }; pci0: pcie@fef08000 { compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0xfef08000 0x1000>; bus-range = <0x0 0xff>; ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <0x18 0x2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2 >; pcie@0 { reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000 0x0 0x40000000 0x01000000 0x0 0x00000000 0x01000000 0x0 0x00000000 0x0 0x00400000>; }; }; };
arch/powerpc/boot/dts/mpc8315erdb.dts +64 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,8 @@ aliases { serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; }; cpus { Loading Loading @@ -349,4 +351,66 @@ pci0: pci@e0008500 { compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; pci1: pcie@e0009000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; reg = <0xe0009000 0x00001000>; ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; bus-range = <0 255>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0 0 0 1 &ipic 1 8 0 0 0 2 &ipic 1 8 0 0 0 3 &ipic 1 8 0 0 0 4 &ipic 1 8>; clock-frequency = <0>; pcie@0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; reg = <0 0 0 0 0>; ranges = <0x02000000 0 0xa0000000 0x02000000 0 0xa0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00800000>; }; }; pci2: pcie@e000a000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; reg = <0xe000a000 0x00001000>; ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; bus-range = <0 255>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0 0 0 1 &ipic 2 8 0 0 0 2 &ipic 2 8 0 0 0 3 &ipic 2 8 0 0 0 4 &ipic 2 8>; clock-frequency = <0>; pcie@0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; reg = <0 0 0 0 0>; ranges = <0x02000000 0 0xc0000000 0x02000000 0 0xc0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00800000>; }; }; };
