Commit f4f5969e authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for ID_DFR0_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_DFR0_EL1 register have an _EL1 suffix,
and use lower-case for feature names where the arm-arm does the same.

The arm-arm has feature names for some of the ID_DFR0_EL1.PerMon encodings.
Use these feature names in preference to the '8_4' indication of the
architecture version they were introduced in.

No functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-12-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 1ecf3dcb

arch/arm64/include/asm/sysreg.h

+11 −13
Original line number Diff line number Diff line
@@ -692,12 +692,10 @@ 
#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48

#endif



#define ID_DFR0_PERFMON_SHIFT		24



#define ID_DFR0_PERFMON_8_0		0x3

#define ID_DFR0_PERFMON_8_1		0x4

#define ID_DFR0_PERFMON_8_4		0x5

#define ID_DFR0_PERFMON_8_5		0x6

#define ID_DFR0_EL1_PerfMon_PMUv3		0x3

#define ID_DFR0_EL1_PerfMon_PMUv3p1		0x4

#define ID_DFR0_EL1_PerfMon_PMUv3p4		0x5

#define ID_DFR0_EL1_PerfMon_PMUv3p5		0x6



#define ID_ISAR4_EL1_SWP_frac_SHIFT		28

#define ID_ISAR4_EL1_PSR_M_SHIFT		24
@@ -760,13 +758,13 @@ 
#define ID_PFR0_EL1_State1_SHIFT	4

#define ID_PFR0_EL1_State0_SHIFT	0



#define ID_DFR0_PERFMON_SHIFT		24

#define ID_DFR0_MPROFDBG_SHIFT		20

#define ID_DFR0_MMAPTRC_SHIFT		16

#define ID_DFR0_COPTRC_SHIFT		12

#define ID_DFR0_MMAPDBG_SHIFT		8

#define ID_DFR0_COPSDBG_SHIFT		4

#define ID_DFR0_COPDBG_SHIFT		0

#define ID_DFR0_EL1_PerfMon_SHIFT	24

#define ID_DFR0_EL1_MProfDbg_SHIFT	20

#define ID_DFR0_EL1_MMapTrc_SHIFT	16

#define ID_DFR0_EL1_CopTrc_SHIFT	12

#define ID_DFR0_EL1_MMapDbg_SHIFT	8

#define ID_DFR0_EL1_CopSDbg_SHIFT	4

#define ID_DFR0_EL1_CopDbg_SHIFT	0



#define ID_PFR2_EL1_SSBS_SHIFT		4

#define ID_PFR2_EL1_CSV3_SHIFT		0

arch/arm64/kernel/cpufeature.c

+7 −7
Original line number Diff line number Diff line
@@ -567,13 +567,13 @@ static const struct arm64_ftr_bits ftr_id_pfr2[] = { 


static const struct arm64_ftr_bits ftr_id_dfr0[] = {

	/* [31:28] TraceFilt */

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),

	ARM64_FTR_END,

};

arch/arm64/kvm/sys_regs.c

+2 −2
Original line number Diff line number Diff line
@@ -1121,8 +1121,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r 
	case SYS_ID_DFR0_EL1:

		/* Limit guests to PMUv3 for ARMv8.4 */

		val = cpuid_feature_cap_perfmon_field(val,

						      ID_DFR0_PERFMON_SHIFT,

						      kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);

						      ID_DFR0_EL1_PerfMon_SHIFT,

						      kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_EL1_PerfMon_PMUv3p4 : 0);

		break;

	}