Unverified Commit f8a9f270 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt 

This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.2, please pull the following:

- Rafal describes the timer/watchdog block for the BCM4908 and BCM6858
  SoCs

- Krzysztof corrects invalid "reg" properties for the memory nodes that
  were off by one digit

- Pierre updates a number of cache Device Tree node properties to be
  schema compliant

* tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: Update cache properties for broadcom
  arm64: dts: broadcom: trim addresses to 8 digits
  arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
  arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer

Link: https://lore.kernel.org/r/20221129191755.542584-2-f.fainelli@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9490ae74 e567e58d

arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ cpu3: cpu@3 { 


		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};
@@ -283,6 +284,11 @@ twd: timer-mfd@400 { 
			#address-cells = <1>;

			#size-cells = <1>;



			timer@0 {

				compatible = "brcm,bcm63138-timer";

				reg = <0x0 0x28>;

			};



			watchdog@28 {

				compatible = "brcm,bcm6345-wdt";

				reg = <0x28 0x8>;

arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ B53_3: cpu@3 { 


		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ B53_1: cpu@1 { 


		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ B53_3: cpu@3 { 


		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ B53_3: cpu@3 { 


		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};