Commit ff3d02b2 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update Knights Landing 

Events are still at version 9:
    https://download.01.org/perfmon/KNL
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf



The addition of a floating-point.json is due to events having
their topic better identified by the converter script.

Tested:

Not tested on a Knights Landing, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...

Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-19-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2782403c

tools/perf/pmu-events/arch/x86/knightslanding/cache.json

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tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json

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[

    {

        "BriefDescription": "Counts the number of floating operations retired that required microcode assists",

        "Counter": "0,1",

        "EventCode": "0xC3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",

        "Counter": "0,1",

        "EventCode": "0xC2",

        "EventName": "UOPS_RETIRED.PACKED_SIMD",

        "PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",

        "SampleAfterValue": "200003",

        "UMask": "0x40"

    },

    {

        "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",

        "Counter": "0,1",

        "EventCode": "0xC2",

        "EventName": "UOPS_RETIRED.SCALAR_SIMD",

        "PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",

        "SampleAfterValue": "200003",

        "UMask": "0x20"

    }

]
 
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tools/perf/pmu-events/arch/x86/knightslanding/frontend.json

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[

    {

        "EventCode": "0x80",

        "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",

        "Counter": "0,1",

        "UMask": "0x3",

        "EventName": "ICACHE.ACCESSES",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.ALL",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",

        "Counter": "0,1",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.COND",

        "SampleAfterValue": "200003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",

        "Counter": "0,1",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.RETURN",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts all instruction fetches, including uncacheable fetches."

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",

        "Counter": "0,1",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "SampleAfterValue": "200003",

        "UMask": "0x3"

    },

    {

        "BriefDescription": "Counts all instruction fetches that hit the instruction cache.",

        "Counter": "0,1",

        "UMask": "0x1",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts all instruction fetches that hit the instruction cache."

        "UMask": "0x1"

    },

    {

        "EventCode": "0x80",

        "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",

        "Counter": "0,1",

        "UMask": "0x2",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding."

        "UMask": "0x2"

    },

    {

        "EventCode": "0xE7",

        "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",

        "Counter": "0,1",

        "UMask": "0x1",

        "EventCode": "0xE7",

        "EventName": "MS_DECODED.MS_ENTRY",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of times the MSROM starts a flow of uops."

        "UMask": "0x1"

    }

]
 
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tools/perf/pmu-events/arch/x86/knightslanding/memory.json

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tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json

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