Commit ff83fec8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-01-20' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Just a pretty regular week for this stage of things, amdgpu and i915,
  along with some msm and misc others.

  fb-helper:
   - switcheroo fix

  msm:
   - kexec shutdown fix
   - fix potential double free

  i915:
   - Reject display plane with height == 0
   - re-disable RC6p on Sandy Bridge
   - Fix hugepages' selftest
   - DG2 hw workarounds
   - switcheroo fix

  vc4:
   - fix a memory leak

  panfrost:
   - Kconfig fix

  amdgpu:
   - Fix display scaling
   - Fix RN/CZN power reporting on some firmware versions
   - Colorspace fixes
   - Fix resource freeing in error case in CS IOCTL
   - Fix warning on driver unload
   - GC11 fixes
   - DCN 3.1.4/5 S/G display workarounds"

* tag 'drm-fixes-2023-01-20' of git://anongit.freedesktop.org/drm/drm: (24 commits)
  drm/amd/display: disable S/G display on DCN 3.1.4
  drm/amd/display: disable S/G display on DCN 3.1.5
  drm/amdgpu: allow multipipe policy on ASICs with one MEC
  drm/amdgpu: correct MEC number for gfx11 APUs
  drm/amd/display: fix issues with driver unload
  drm/amdgpu: fix amdgpu_job_free_resources v2
  drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix
  drm/amd/display: Calculate output_color_space after pixel encoding adjustment
  drm/amdgpu: fix cleaning up reserved VMID on release
  drm/amdgpu: Correct the power calcultion for Renior/Cezanne.
  drm/amd/display: Fix set scaling doesn's work
  drm/i915: Remove unused variable
  drm/i915/dg2: Introduce Wa_18019271663
  drm/i915/dg2: Introduce Wa_18018764978
  drm/fb-helper: Set framebuffer for vga-switcheroo clients
  drm/i915: Allow switching away via vga-switcheroo if uninitialized
  drm/i915/selftests: Unwind hugepages to drop wakeref on error
  drm/i915: re-disable RC6p on Sandy Bridge
  drm/panfrost: fix GENERIC_ATOMIC64 dependency
  drm/i915/display: Check source height is > 0
  ...
parents 35929dae 3f30a6e6

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -156,6 +156,9 @@ static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) 
		return amdgpu_compute_multipipe == 1;

		return amdgpu_compute_multipipe == 1;

	}

	}





	if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))

		return true;



	/* FIXME: spreading the queues across pipes causes perf regressions

	/* FIXME: spreading the queues across pipes causes perf regressions

	 * on POLARIS11 compute workloads */

	 * on POLARIS11 compute workloads */

	if (adev->asic_type == CHIP_POLARIS11)

	if (adev->asic_type == CHIP_POLARIS11)

drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -497,6 +497,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, 
	    !--id_mgr->reserved_use_count) {

	    !--id_mgr->reserved_use_count) {

		/* give the reserved ID back to normal round robin */

		/* give the reserved ID back to normal round robin */

		list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);

		list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);

		id_mgr->reserved = NULL;

	}

	}

	vm->reserved_vmid[vmhub] = false;

	vm->reserved_vmid[vmhub] = false;

	mutex_unlock(&id_mgr->lock);

	mutex_unlock(&id_mgr->lock);

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -161,8 +161,14 @@ void amdgpu_job_free_resources(struct amdgpu_job *job) 
	struct dma_fence *f;

	struct dma_fence *f;

	unsigned i;

	unsigned i;





	/* use sched fence if available */

	/* Check if any fences where initialized */

	f = job->base.s_fence ? &job->base.s_fence->finished :  &job->hw_fence;

	if (job->base.s_fence && job->base.s_fence->finished.ops)

		f = &job->base.s_fence->finished;

	else if (job->hw_fence.ops)

		f = &job->hw_fence;

	else

		f = NULL;



	for (i = 0; i < job->num_ibs; ++i)

	for (i = 0; i < job->num_ibs; ++i)

		amdgpu_ib_free(ring->adev, &job->ibs[i], f);

		amdgpu_ib_free(ring->adev, &job->ibs[i], f);

}

}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+9 −2
Original line number Original line Diff line number Diff line
@@ -1287,10 +1287,8 @@ static int gfx_v11_0_sw_init(void *handle) 




	switch (adev->ip_versions[GC_HWIP][0]) {

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(11, 0, 0):

	case IP_VERSION(11, 0, 0):

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 2):

	case IP_VERSION(11, 0, 2):

	case IP_VERSION(11, 0, 3):

	case IP_VERSION(11, 0, 3):

	case IP_VERSION(11, 0, 4):

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;

		adev->gfx.me.num_queue_per_pipe = 1;
@@ -1298,6 +1296,15 @@ static int gfx_v11_0_sw_init(void *handle) 
		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

		break;

		break;

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 4):

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;

		adev->gfx.mec.num_mec = 1;

		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

		break;

	default:

	default:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+4 −10
Original line number Original line Diff line number Diff line
@@ -1503,8 +1503,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
		case IP_VERSION(3, 0, 1):

		case IP_VERSION(3, 0, 1):

		case IP_VERSION(3, 1, 2):

		case IP_VERSION(3, 1, 2):

		case IP_VERSION(3, 1, 3):

		case IP_VERSION(3, 1, 3):

		case IP_VERSION(3, 1, 4):

		case IP_VERSION(3, 1, 5):

		case IP_VERSION(3, 1, 6):

		case IP_VERSION(3, 1, 6):

			init_data.flags.gpu_vm_support = true;

			init_data.flags.gpu_vm_support = true;

			break;

			break;
@@ -1730,10 +1728,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) 
		adev->dm.vblank_control_workqueue = NULL;

		adev->dm.vblank_control_workqueue = NULL;

	}

	}





	for (i = 0; i < adev->dm.display_indexes_num; i++) {

		drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);

	}



	amdgpu_dm_destroy_drm_device(&adev->dm);

	amdgpu_dm_destroy_drm_device(&adev->dm);





#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)

#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
@@ -5311,8 +5305,6 @@ static void fill_stream_properties_from_drm_display_mode( 




	timing_out->aspect_ratio = get_aspect_ratio(mode_in);

	timing_out->aspect_ratio = get_aspect_ratio(mode_in);





	stream->output_color_space = get_output_color_space(timing_out);



	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;

	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;

	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
@@ -5323,6 +5315,8 @@ static void fill_stream_properties_from_drm_display_mode( 
			adjust_colour_depth_from_display_info(timing_out, info);

			adjust_colour_depth_from_display_info(timing_out, info);

		}

		}

	}

	}



	stream->output_color_space = get_output_color_space(timing_out);

}

}





static void fill_audio_info(struct audio_info *audio_info,

static void fill_audio_info(struct audio_info *audio_info,
@@ -9530,8 +9524,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
			goto fail;

			goto fail;

		}

		}





		if (dm_old_con_state->abm_level !=

		if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||

		    dm_new_con_state->abm_level)

		    dm_old_con_state->scaling != dm_new_con_state->scaling)

			new_crtc_state->connectors_changed = true;

			new_crtc_state->connectors_changed = true;

	}

	}