Commits · 0d7a5328dba0d3e299d7d611e4ec059b8cab4f38 · jan.koester / Linux · GitLab

Apr 12, 2017
- Merge tag 'amlogic-clk' of... · 0d7a5328
  Michael Turquette authored Apr 12, 2017
  0d7a5328
- clk: aggregate return codes of notify chains · 17c34c56
  Peter De Schrijver authored Mar 21, 2017
  17c34c56
- clk: add clk_possible_parents debugfs file · 92031575
  Peter De Schrijver authored Mar 21, 2017
  92031575
- clk: imx: correct uart4_serial clock name in driver for i.MX6UL · 19057195
  Robin van der Gracht authored Mar 06, 2017
  19057195
- clk: zte: Mark pll config tables as const · 15a2a14b
  Stephen Boyd authored Apr 07, 2017
  15a2a14b
- clk: zte: add pll_vga clock for zx296718 · a90099da
  Shawn Guo authored Mar 21, 2017
  a90099da
- clk: zte: pd_bit is not 0 on zx296718 · ee249cbe
  Shawn Guo authored Mar 21, 2017
  ee249cbe
- clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks · 5790d801
  Shawn Guo authored Mar 21, 2017
  5790d801
- clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock · cf091ee9
  Robin van der Gracht authored Mar 03, 2017
  cf091ee9
- Merge tag 'tegra-for-4.12-clk' of... · 72be2d5f
  Michael Turquette authored Apr 12, 2017
  72be2d5f
- cs-2000-cp: keep Reserved bit on each register · 1f9dfd7a
  Kuninori Morimoto authored Apr 05, 2017
  1f9dfd7a
- clk: qcom: msm8996: Fix the vfe1 powerdomain name · a62ca337
  Rajendra Nayak authored Mar 23, 2017
  a62ca337
- clk: stm32f4: fix timeout management for pll and ready gate · ac03d8b3
  Gabriel Fernandez authored Mar 16, 2017
  ac03d8b3
- clk: iproc: Remove redundant check · d5a0945f
  Ray Jui authored Apr 05, 2017
  d5a0945f
- Merge tag 'v4.12-rockchip-clk1' of... · 55798360
  Michael Turquette authored Apr 12, 2017
  55798360
- Merge tag 'clk-renesas-for-v4.12-tag2' of... · 0d4ae360
  Michael Turquette authored Apr 12, 2017
  0d4ae360
- Merge branch 'clk-fixes' into clk-next · f37753e2
  Stephen Boyd authored Apr 04, 2017
  f37753e2
- clk: stm32f4: fix: exclude values 0 and 1 for PLLQ · ef189104
  Gabriel Fernandez authored Mar 16, 2017
  ef189104
- Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-next · 4641d6a5
  Stephen Boyd authored Apr 04, 2017
  4641d6a5
- clk: hi6220: add debug APB clock · b0459491
  Leo Yan authored Mar 26, 2017
  b0459491
Apr 04, 2017
- Merge branch 'v4.12/clk-drivers' into v4.12/clk · 3a429818
  Kevin Hilman authored Apr 04, 2017
  3a429818
- clk: meson-gxbb: Add GXL/GXM GP0 Variant · 0d48fc55
  Neil Armstrong authored Mar 22, 2017
  0d48fc55
- clk: meson-gxbb: Add GP0 PLL init parameters · e194401c
  Neil Armstrong authored Mar 22, 2017
  e194401c
- clk: meson: Add support for parameters for specific PLLs · 45fcbec7
  Neil Armstrong authored Mar 22, 2017
  45fcbec7
- clk: meson-gxbb: Add MALI clocks · fac9a55b
  Neil Armstrong authored Mar 22, 2017
  fac9a55b
- dt-bindings: clock: gxbb-clkc: Add GXL compatible variant · 92c2cc5d
  Neil Armstrong authored Mar 22, 2017
  92c2cc5d
- clk: meson-gxbb: Expose GP0 dt-bindings clock id · 7d33d60b
  Neil Armstrong authored Mar 22, 2017
  7d33d60b
- clk: meson-gxbb: Add MALI clock IDS · 5c65eec3
  Neil Armstrong authored Mar 22, 2017
  5c65eec3
- dt-bindings: clk: gxbb: expose i2s output clock gates · 28f6c583
  Jerome Brunet authored Mar 09, 2017
  28f6c583
- clk: tegra: Don't reset PLL-CX if it is already enabled · 1116d5a7
  Jon Hunter authored Mar 27, 2017
  1116d5a7
- clk: tegra: Add missing Tegra210 clocks · 88da44c5
  Peter De Schrijver authored Mar 22, 2017
  88da44c5
- clk: tegra: Propagate clk_out_x rate to parent · a63b6186
  Alex Frid authored Mar 22, 2017
  a63b6186
Mar 30, 2017
- clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 · bb195306
  Geert Uytterhoeven authored Mar 10, 2017
  bb195306
- clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 · 5573d194
  Geert Uytterhoeven authored Sep 29, 2016
  5573d194
- clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions · 89f1b1c6
  Geert Uytterhoeven authored Sep 29, 2016
  89f1b1c6
- clk: renesas: cpg-mssr: Add support for fixing up clock tables · 48d0341e
  Geert Uytterhoeven authored Sep 29, 2016
  48d0341e
Mar 27, 2017
- clk: meson: mpll: correct N2 maximum value · b68fb787
  Jerome Brunet authored Mar 09, 2017
  b68fb787
- clk: meson8b: add the mplls clocks 0, 1 and 2 · b778f745
  Jerome Brunet authored Mar 09, 2017
  b778f745
- clk: meson: gxbb: mpll: use rw operation · 05b43aa2
  Jerome Brunet authored Mar 09, 2017
  05b43aa2
- clk: meson: mpll: add rw operation · 007e6e5c
  Jerome Brunet authored Mar 09, 2017
  007e6e5c