Commits · 1f4b840983ffbd7053b5c2219deaf62b4b8a3c12 · jan.koester / Linux · GitLab

Jun 21, 2015
- MIPS: JZ4740: Call jz4740_clock_init earlier · 1f4b8409
  Paul Burton authored May 24, 2015
  1f4b8409
- MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip · 44e08e70
  Paul Burton authored May 24, 2015
  44e08e70
- MIPS: JZ4740: support newer SoC interrupt controllers · 24ccfa06
  Paul Burton authored May 24, 2015
  24ccfa06
- MIPS: JZ4740: Avoid JZ4740-specific naming · 2da01884
  Paul Burton authored May 24, 2015
  2da01884
- MIPS: JZ4740: read intc base address from DT · 3aa94590
  Paul Burton authored May 24, 2015
  3aa94590
- MIPS: JZ4740: define IRQ numbers based on number of intc IRQs · ad68f8d3
  Paul Burton authored May 24, 2015
  ad68f8d3
- MIPS: JZ4740: support >32 interrupts · 943d69c6
  Paul Burton authored May 24, 2015
  943d69c6
- MIPS: JZ4740: Remove jz_intc_base global · fe778ece
  Paul Burton authored May 24, 2015
  fe778ece
- MIPS: JZ4740: drop intc debugfs code · 2aabd281
  Paul Burton authored May 24, 2015
  2aabd281
- MIPS: JZ4740: register an irq_domain for the interrupt controller · 638c8851
  Paul Burton authored May 24, 2015
  638c8851
- MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT · 69ce4b22
  Paul Burton authored May 24, 2015
  69ce4b22
- MIPS: JZ4740: probe interrupt controller via DT · adbdce77
  Paul Burton authored May 24, 2015
  adbdce77
- devicetree: document Ingenic SoC interrupt controller binding · 5f408ebf
  Paul Burton authored May 24, 2015
  5f408ebf
- MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c · 0e81db8f
  Paul Burton authored May 24, 2015
  0e81db8f
- MIPS: JZ4740: use generic plat_irq_dispatch · 2974a356
  Paul Burton authored May 24, 2015
  2974a356
- MIPS: JZ4740: probe CPU interrupt controller via DT · 8e8261eb
  Paul Burton authored May 24, 2015
  8e8261eb
- IRQCHIP: irq_cpu: declare irqchip table entry · 892b8cf0
  Paul Burton authored May 24, 2015
  892b8cf0
- MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip. · 67e38cf2
  Ralf Baechle authored May 26, 2015
  67e38cf2
- MIPS: JZ4740: require & include DT · ffb1843d
  Paul Burton authored May 24, 2015
  ffb1843d
- MIPS: ingenic: Add newer vendor IDs · 252617a4
  Paul Burton authored May 24, 2015
  252617a4
- MIPS: JZ4740: introduce CONFIG_MACH_INGENIC · de361e8b
  Paul Burton authored May 24, 2015
  de361e8b
- devicetree/bindings: add Qi Hardware vendor prefix · 2d06fe53
  Paul Burton authored May 24, 2015
  2d06fe53
- devicetree/bindings: add Ingenic Semiconductor vendor prefix · f289cc7b
  Paul Burton authored May 24, 2015
  f289cc7b
- MIPS: DEC: Update CPU overrides · bc4f12e6
  Maciej W. Rozycki authored May 27, 2015
  bc4f12e6
- MIPS: netlogic: remove unnecessary MTD partition probe specification · cc23cafe
  Brian Norris authored May 18, 2015
  cc23cafe
- MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation · 9a20b092
  Maciej W. Rozycki authored May 27, 2015
  9a20b092
- MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init' · 3bcb03f3
  Maciej W. Rozycki authored May 27, 2015
  3bcb03f3
- MIPS: tlb-r3k: Also invalidate wired TLB entries on boot · dbfbf60f
  Maciej W. Rozycki authored May 27, 2015
  dbfbf60f
- MIPS: dump_tlb: Take XPA into account · 24ca1d98
  James Hogan authored May 19, 2015
  24ca1d98
- MIPS: dump_tlb: Take RI/XI bits into account · c2bc435e
  James Hogan authored May 19, 2015
  c2bc435e
- MIPS: dump_tlb: Take EHINV bit into account · decebccd
  James Hogan authored May 19, 2015
  decebccd
- MIPS: dump_tlb: Take global bit into account · 48269c78
  James Hogan authored May 19, 2015
  48269c78
- MIPS: dump_tlb: Make use of EntryLo bit definitions · d7f5499d
  James Hogan authored May 19, 2015
  d7f5499d
- MIPS: dump_tlb: Refactor TLB matching · d1ce483e
  James Hogan authored May 19, 2015
  d1ce483e
- MIPS: dump_tlb: Use tlbr hazard macros · 137877e4
  James Hogan authored May 19, 2015
  137877e4
- MIPS: mipsregs.h: Add EntryLo bit definitions · 8ab6abcb
  James Hogan authored May 19, 2015
  8ab6abcb
- MIPS: hazards: Add hazard macros for tlb read · e50f0e31
  James Hogan authored May 19, 2015
  e50f0e31
- MIPS: Add SysRq operation to dump TLBs on all CPUs · d1e9a4f5
  James Hogan authored May 19, 2015
  d1e9a4f5
- MIPS: traps: print Exception Code in __show_regs() · 37dd3818
  Petri Gynther authored May 08, 2015
  37dd3818
- MIPS: BCM47xx: Read board info for all bcma buses · 26238994
  Rafał Miłecki authored May 12, 2015
  26238994