Commits · 3440d265857b411a13ed8f67814a29fa2011cdb3 · jan.koester / Linux · GitLab

Jan 31, 2013
- drm/i915: extract hw ppgtt setup/cleanup code · 3440d265
  Daniel Vetter authored Jan 24, 2013
  3440d265
- drm/i915: pte_encode is gen6+ · 960e3e42
  Daniel Vetter authored Jan 24, 2013
  960e3e42
- drm/i915: vfuncs for ppgtt · def886c3
  Daniel Vetter authored Jan 24, 2013
  def886c3
- drm/i915: vfuncs for gtt_clear_range/insert_entries · 7faf1ab2
  Daniel Vetter authored Jan 24, 2013
  7faf1ab2
- drm/i915: Error state should print /sys/kernel/debug · 2f86f191
  Ben Widawsky authored Jan 28, 2013
  2f86f191
- drm/i915: move DP save/restore into i915_ums.c · a65e827d
  Daniel Vetter authored Jan 25, 2013
  a65e827d
- drm/i915: dont save/restore VGA state for kms · 44cec740
  Daniel Vetter authored Jan 25, 2013
  44cec740
- drm/i915: extract ums suspend/resume into i915_ums.c · d8157a36
  Daniel Vetter authored Jan 25, 2013
  d8157a36
Jan 28, 2013
- drm/i915: move modeset checks out of save/restore_modeset_reg · 2e9723a3
  Daniel Vetter authored Jan 25, 2013
  2e9723a3
- drm/i915: Implement WaVSRefCountFullforceMissDisable · 41c0b3a8
  Ben Widawsky authored Jan 26, 2013
  41c0b3a8
Jan 27, 2013
- drm/i915: turn on the power well before suspending · cb10799c
  Paulo Zanoni authored Jan 25, 2013
  cb10799c
- drm/i915: set TRANSCODER_EDP even earlier · cc464b2a
  Paulo Zanoni authored Jan 25, 2013
  cc464b2a
Jan 26, 2013
- drm/i915: only disable enabled planes on intel_fb_restore_mode · 56e5a3f0
  Paulo Zanoni authored Jan 25, 2013
  56e5a3f0
- drm/i915: fix intel_init_power_wells · fa42e23c
  Paulo Zanoni authored Jan 25, 2013
  fa42e23c
- drm/i915: SWF screatch registers need an offset on VLV · 80a75f7c
  Ville Syrjälä authored Jan 24, 2013
  80a75f7c
- drm/i915: Include display_mmio_offset in sequencer index/data registers · 56a12a50
  Ville Syrjälä authored Jan 25, 2013
  56a12a50
- drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV · 67cfc203
  Ville Syrjälä authored Jan 25, 2013
  67cfc203
- drm/i915: VLV doesn't have SDVO · 9d5f78fb
  Ville Syrjälä authored Jan 25, 2013
  9d5f78fb
- drm/i915: Always use adpa_reg · ca54b810
  Ville Syrjälä authored Jan 25, 2013
  ca54b810
- drm/i915: PLL registers need an offset on VLV · fc2de409
  Ville Syrjälä authored Jan 25, 2013
  fc2de409
Jan 24, 2013
- drm/i915: Set display_mmio_offset for VLV · fba5d532
  Ville Syrjälä authored Jan 24, 2013
  fba5d532
- drm/i915: GPIO/GMBUS registers need an offset on VLV · d8112150
  Ville Syrjälä authored Jan 24, 2013
  d8112150
- drm/i915: DPIO registers are VLV only and need an offset · 54d9d493
  Ville Syrjälä authored Jan 24, 2013
  54d9d493
- drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers · ff763010
  Ville Syrjälä authored Jan 24, 2013
  ff763010
- drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable · 07ec7ec5
  Ville Syrjälä authored Jan 24, 2013
  07ec7ec5
- drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset · d88b2270
  Ville Syrjälä authored Jan 24, 2013
  d88b2270
- drm/i915: Pipe palette registers need an offset on VLV · 4b059985
  Ville Syrjälä authored Jan 24, 2013
  4b059985
- drm/i915: Pipe timing registers need an offset on VLV · 4e8e7eb7
  Ville Syrjälä authored Jan 24, 2013
  4e8e7eb7
- drm/i915: PORT_HOTPLUG registers need an offset on VLV · 67d62c57
  Ville Syrjälä authored Jan 24, 2013
  67d62c57
- drm/i915: Panel fitter registers need an offset on VLV · 7e470abf
  Ville Syrjälä authored Jan 24, 2013
  7e470abf
- drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset · b41fbda1
  Ville Syrjälä authored Jan 24, 2013
  b41fbda1
- drm/i915: DSPFW registers need an offset on VLV · 90f7da3f
  Ville Syrjälä authored Jan 24, 2013
  90f7da3f
- drm/i915: VLV_DDL is VLV only and needs an offset · 8f6d8ee9
  Ville Syrjälä authored Jan 24, 2013
  8f6d8ee9
- drm/i915: Cursor registers need an offset on VLV · 9dc33f31
  Ville Syrjälä authored Jan 24, 2013
  9dc33f31
- drm/i915: Pipe registers need an offset on VLV · 0c3870ee
  Ville Syrjälä authored Jan 24, 2013
  0c3870ee
- drm/i915: Primary plane registers need an offset on VLV · 895abf0c
  Ville Syrjälä authored Jan 24, 2013
  895abf0c
- drm/i915: PIPE M/N registers need an offset on VLV · aab17139
  Ville Syrjälä authored Jan 24, 2013
  aab17139
- drm/i915: VLV_VIDEO_DIP_CTL is for VLV only · b906487c
  Ville Syrjälä authored Jan 24, 2013
  b906487c
- drm/i915: Per-pipe PP registers are for VLV only · f12c47b2
  Ville Syrjälä authored Jan 24, 2013
  f12c47b2
- drm/i915: AUD_VID_DID needs an offset on VLV · f4ba9f81
  Ville Syrjälä authored Jan 24, 2013
  f4ba9f81