Commits · 3b0da91688b64290df7b6a31b515a8c903675525 · jan.koester / Linux · GitLab

Nov 14, 2017
- Merge branch 'clk-sunxi' into clk-next · 3b0da916
  Stephen Boyd authored Nov 14, 2017
  3b0da916
- Merge branch 'clk-hikey' into clk-next · bdf6bfb3
  Stephen Boyd authored Nov 14, 2017
  bdf6bfb3
- Merge tag 'tegra-for-4.15-clk-2' of... · 042e2e9c
  Stephen Boyd authored Nov 14, 2017
  042e2e9c
- clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' · 3320f39b
  Shawn Guo authored Sep 27, 2017
  3320f39b
- clk: hisilicon: Delete an error message for a failed memory allocation in... · 90c42090
  Markus Elfring authored Sep 26, 2017
  90c42090
- clk: hi3660: fix incorrect uart3 clock freqency · d33fb1b9
  Zhong Kaihua authored Aug 07, 2017
  d33fb1b9
Nov 02, 2017
- clk: sunxi: explicitly request exclusive reset control · cb92a19b
  Philipp Zabel authored Jul 19, 2017
  cb92a19b
- clk: sunxi: fix build warning · 02e0114a
  Corentin LABBE authored Oct 24, 2017
  02e0114a
Nov 01, 2017
- clk: hi6220: mark clock cs_atb_syspll as critical · d2a3671e
  Leo Yan authored Sep 01, 2017
  d2a3671e
- clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() · 22ef01a2
  Nicolin Chen authored Sep 15, 2017
  22ef01a2
- clk: tegra: dfll: Fix drvdata overwriting issue · 1752c9ee
  Nicolin Chen authored Oct 12, 2017
  1752c9ee
- clk: tegra: Fix cclk_lp divisor register · 54eff226
  Michał Mirosław authored Sep 19, 2017
  54eff226
- clk: tegra: Bump SCLK clock rate to 216 MHz · d80a32fe
  Dmitry Osipenko authored Oct 04, 2017
  d80a32fe
- clk: tegra: Use common definition of APBDMA clock gate · 5a6b184a
  Dmitry Osipenko authored Oct 04, 2017
  5a6b184a
- clk: tegra: Correct parent of the APBDMA clock · 3ff46fd0
  Dmitry Osipenko authored Oct 04, 2017
  3ff46fd0
- clk: tegra: Add AHB DMA clock entry · 899f8095
  Dmitry Osipenko authored Oct 04, 2017
  899f8095
- clk: tegra: Mark APB clock as critical · 109eba2e
  Jon Hunter authored Oct 23, 2017
  109eba2e
Oct 31, 2017
- Merge tag 'v4.15-rockchip-clk-1' of... · 6705fc94
  Stephen Boyd authored Oct 31, 2017
  6705fc94
- Merge tag 'clk-renesas-for-v4.15-tag2' of... · b177571b
  Stephen Boyd authored Oct 31, 2017
  b177571b
- Merge tag 'meson-clk-for-4.15' of git://github.com/baylibre/clk-meson into clk-next · 319663c7
  Stephen Boyd authored Oct 31, 2017
  319663c7
- Merge tag 'sunxi-clk-for-4.15' of... · ffc3eb6f
  Stephen Boyd authored Oct 31, 2017
  ffc3eb6f
- Merge tag 'clk-v4.15-exynos-pm' of... · ae74ac08
  Stephen Boyd authored Oct 30, 2017
  ae74ac08
Oct 25, 2017
- Merge tag 'clk-v4.15-samsung' of... · faa865f1
  Stephen Boyd authored Oct 25, 2017
  faa865f1
- Merge tag 'clk-renesas-for-v4.15-tag1' of... · f09a6b86
  Stephen Boyd authored Oct 25, 2017
  f09a6b86
Oct 20, 2017
- clk: renesas: rcar-gen3: Restore R clock during resume · 3f7a4d08
  Geert Uytterhoeven authored Jun 28, 2017
  3f7a4d08
- clk: renesas: rcar-gen3: Restore SDHI clocks during resume · 9f55b17f
  Geert Uytterhoeven authored Jun 21, 2017
  9f55b17f
- clk: renesas: div6: Restore clock state during resume · 9f8c71e5
  Geert Uytterhoeven authored Jun 21, 2017
  9f8c71e5
- clk: renesas: cpg-mssr: Add support to restore core clocks during resume · 1f4023cd
  Geert Uytterhoeven authored Jun 21, 2017
  1f4023cd
- clk: renesas: cpg-mssr: Restore module clocks during resume · 56086910
  Geert Uytterhoeven authored Jun 07, 2017
  56086910
- MAINTAINERS: Add git repository to Renesas clock driver section · d9341f2b
  Geert Uytterhoeven authored Sep 13, 2017
  d9341f2b
- clk: renesas: cpg-mssr: Add du1 clock to R8A7745 · 9dc0ddee
  Fabrizio Castro authored Oct 13, 2017
  9dc0ddee
- clk: renesas: rz: clk-rz is meant for RZ/A1 · d454cecc
  Geert Uytterhoeven authored Oct 12, 2017
  d454cecc
- clk: meson: gxbb: Add VPU and VAPB clocks data · 762a1f20
  Neil Armstrong authored Oct 16, 2017
  762a1f20
- clk: meson: gxbb: Add VPU and VAPB clockids · 4cf8f811
  Neil Armstrong authored Oct 16, 2017
  4cf8f811
Oct 19, 2017
- clk: tegra: Make tegra_clk_pll_params __ro_after_init · d83b26e0
  Bhumika Goyal authored Oct 03, 2017
  d83b26e0
- clk: tegra: Fix sor1_out clock implementation · bc2e4d29
  Thierry Reding authored Aug 30, 2017
  bc2e4d29
- clk: tegra: Use tegra_clk_register_periph_data() · 1d7e2c8e
  Thierry Reding authored Aug 30, 2017
  1d7e2c8e
- clk: tegra: Add peripheral clock registration helper · 8be95190
  Thierry Reding authored Aug 30, 2017
  8be95190
- clk: tegra: Check BPMP response return code · 231ca2e5
  Timo Alho authored Sep 07, 2017
  231ca2e5
- Merge branch 'for-4.15/firmware' into for-4.15/clk · 8f43ff6b
  Thierry Reding authored Oct 19, 2017
  
  8f43ff6b