Commits · 3b306f6f3a03c285a7044350d263cb9251def49d · jan.koester / Linux · GitLab

Oct 31, 2018
- Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32" · 3b306f6f
  Palmer Dabbelt authored Oct 26, 2018
  3b306f6f
Oct 23, 2018
- RISC-V: SMP cleanup and new features · d26c4bbf
  Palmer Dabbelt authored Oct 22, 2018
  d26c4bbf
- RISC-V: Fix some RV32 bugs and build failures · a6de21ba
  Palmer Dabbelt authored Oct 22, 2018
  a6de21ba
- riscv: Add support to no-FPU systems · 4e4101cf
  Palmer Dabbelt authored Oct 22, 2018
  4e4101cf
- RISC-V: Cosmetic menuconfig changes · aef53f97
  Nick Kossifidis authored Sep 20, 2018
  aef53f97
- riscv: move GCC version check for ARCH_SUPPORTS_INT128 to Kconfig · ee592884
  Masahiro Yamada authored Aug 24, 2018
  ee592884
- RISC-V: remove the unused return_to_handler export · f31b8de9
  Christoph Hellwig authored Sep 21, 2018
  f31b8de9
- RISC-V: Add futex support. · b90edb33
  Jim Wilson authored Oct 16, 2018
  b90edb33
- RISC-V: Add FP register ptrace support for gdb. · b8c8a959
  Jim Wilson authored Oct 17, 2018
  b8c8a959
- RISC-V: Mask out the F extension on systems without D · 86e581e3
  Palmer Dabbelt authored Aug 27, 2018
  86e581e3
- RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} · 1760debb
  Palmer Dabbelt authored Jul 24, 2018
  1760debb
- RISC-V: Show IPI stats · 8b20d2db
  Anup Patel authored Oct 02, 2018
  8b20d2db
- RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo · 4b26d22f
  Anup Patel authored Oct 02, 2018
  4b26d22f
- RISC-V: Use Linux logical CPU number instead of hartid · f99fb607
  Atish Patra authored Oct 02, 2018
  f99fb607
- RISC-V: Add logical CPU indexing for RISC-V · 6825c7a8
  Atish Patra authored Oct 02, 2018
  6825c7a8
- RISC-V: Use WRITE_ONCE instead of direct access · a37d56fc
  Atish Patra authored Oct 02, 2018
  a37d56fc
- RISC-V: Use mmgrab() · 46373cb4
  Palmer Dabbelt authored Oct 02, 2018
  46373cb4
- RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu · 177fae45
  Palmer Dabbelt authored Oct 02, 2018
  177fae45
- RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid · b2f8cfa7
  Palmer Dabbelt authored Oct 02, 2018
  b2f8cfa7
- RISC-V: Provide a cleaner raw_smp_processor_id() · 9639a443
  Palmer Dabbelt authored Oct 02, 2018
  9639a443
- RISC-V: Disable preemption before enabling interrupts · 6db170ff
  Atish Patra authored Oct 02, 2018
  6db170ff
- RISC-V: Comment on the TLB flush in smp_callin() · b18d6f05
  Palmer Dabbelt authored Oct 02, 2018
  b18d6f05
- RISC-V: Filter ISA and MMU values in cpuinfo · 19ccf29b
  Palmer Dabbelt authored Oct 02, 2018
  19ccf29b
- RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} · 566d6c42
  Palmer Dabbelt authored Oct 02, 2018
  566d6c42
- RISC-V: No need to pass scause as arg to do_IRQ() · 1ed4237a
  Anup Patel authored Oct 02, 2018
  1ed4237a
- RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap · 827a4381
  Vincent Chen authored Oct 02, 2018
  827a4381
- RISC-V: Select GENERIC_LIB_UMODDI3 on RV32 · 757331db
  Zong Li authored Oct 02, 2018
  757331db
- lib: Add umoddi3 and udivmoddi4 of GCC library routines · 6315730e
  Zong Li authored Oct 02, 2018
  6315730e
- RISC-V: Use swiotlb on RV64 only · 51858aaf
  Zong Li authored Oct 02, 2018
  51858aaf
- RISC-V: Build tishift only on 64-bit · 7f47c73b
  Zong Li authored Oct 02, 2018
  7f47c73b
- Auto-detect whether a FPU exists · 9411ec60
  Alan Kao authored Oct 09, 2018
  9411ec60
- Allow to disable FPU support · 9671f706
  Alan Kao authored Oct 09, 2018
  9671f706
- Cleanup ISA string setting · e8be5302
  Alan Kao authored Oct 09, 2018
  e8be5302
- Refactor FPU code in signal setup/return procedures · 007f5c35
  Alan Kao authored Oct 09, 2018
  007f5c35
- Extract FPU context operations from entry.S · e68ad867
  Alan Kao authored Oct 09, 2018
  e68ad867
Oct 22, 2018
- Linux 4.19 · 84df9525
  Greg Kroah-Hartman authored Oct 22, 2018
  
  View commits for tag v4.19 v4.19
  
  84df9525
- MAINTAINERS: Add an entry for the code of conduct · 8e630c31
  Greg Kroah-Hartman authored Oct 19, 2018
  8e630c31
- Code of Conduct: Change the contact email address · f3f76d64
  Greg Kroah-Hartman authored Oct 19, 2018
  f3f76d64
- Code of Conduct Interpretation: Put in the proper URL for the committee · d117a854
  Greg Kroah-Hartman authored Oct 19, 2018
  d117a854
- Code of Conduct: Provide links between the two documents · f7e58584
  Greg Kroah-Hartman authored Oct 19, 2018
  f7e58584