Commits · 6ac0483b35bfc7546398d1198b65ed7be17f3cc5 · jan.koester / Linux · GitLab

Nov 17, 2014
- drm/i915: Propagate invalid setcrtc cloning errors back to userspace · 6ac0483b
  Matt Roper authored Nov 17, 2014
  6ac0483b
- drm/i915/skl: Use the pipe config DPLL tracking to query the link clock · 134ffa44
  Damien Lespiau authored Nov 14, 2014
  134ffa44
- drm/i915/skl: Set the eDP link rate on DPLL0 · 5416d871
  Damien Lespiau authored Nov 14, 2014
  5416d871
- drm/i915: Add PSR docbook · b2b89f55
  Rodrigo Vivi authored Nov 14, 2014
  b2b89f55
- drm/i915: Introduce intel_psr.c · 0bc12bcb
  Rodrigo Vivi authored Nov 14, 2014
  0bc12bcb
- drm/i915: Make dp aux pack/unpack public outside intel_dp.c · a4f1289e
  Rodrigo Vivi authored Nov 14, 2014
  a4f1289e
- drm/i915: Drop WaRsForcewakeWaitTC0:vlv · 2fe486c7
  Ville Syrjälä authored Nov 13, 2014
  2fe486c7
- drm/i915: Drop the HSW special case from __gen6_gt_wait_for_thread_c0() · eb88bd1b
  Ville Syrjälä authored Nov 13, 2014
  eb88bd1b
- drm/i915/skl: Remove spurious warn in get_ddi_pll() · f5f7d3c6
  Damien Lespiau authored Nov 14, 2014
  f5f7d3c6
- drm/i915: Change CHV SKU400 GPU freq divider to 10 · ab3fb157
  Ville Syrjälä authored Nov 10, 2014
  ab3fb157
- drm/i915: Add missing newline to 'DDR speed' debug messages · 80b83b62
  Ville Syrjälä authored Nov 10, 2014
  80b83b62
- drm/i915: Refactor vlv/chv GPU frequency divider setup · dd06f88c
  Ville Syrjälä authored Nov 10, 2014
  dd06f88c
- drm/i915: Improve PCBR debug information · ce611ef8
  Ville Syrjälä authored Nov 07, 2014
  ce611ef8
- drm/i915: Warn if GPLL isn't used on vlv/chv · 8d40c3ae
  Ville Syrjälä authored Nov 07, 2014
  8d40c3ae
- drm/i915: Add a name for the Punit GPLLENABLE bit · c8e9627d
  Ville Syrjälä authored Nov 07, 2014
  c8e9627d
- drm/i915: Silence valleyview_set_rps() · 9a3b9c7a
  Ville Syrjälä authored Nov 07, 2014
  9a3b9c7a
- drm/i915: Reinit display irqs and hpd from chv pipe-a power well · afd6275d
  Ville Syrjälä authored Oct 30, 2014
  afd6275d
Nov 14, 2014
- drm/i915: Fix comments about CHV snoop behaviour · cf3d262e
  Ville Syrjälä authored Nov 14, 2014
  cf3d262e
- drm/i915: Use vlv display irq setup code for chv · c2b66797
  Ville Syrjälä authored Oct 30, 2014
  c2b66797
- drm/i915: Refactor vlv_display_irq_uninstall() · 8ea0be4f
  Ville Syrjälä authored Oct 30, 2014
  8ea0be4f
- drm/i915/skl: Don't allow disabling ppgtt and execlists on gen9+ · 70ee45e1
  Damien Lespiau authored Nov 14, 2014
  70ee45e1
- drm/i915/skl: Fix big integer constant sparse warning · 21318cce
  Damien Lespiau authored Nov 14, 2014
  21318cce
- drm/i915: Let's hope future platforms will use the same WM code as SKL · f5ed50cb
  Damien Lespiau authored Nov 13, 2014
  f5ed50cb
- drm/i915/skl: Use correct use counters for force wakes · 6e7cc470
  Tvrtko Ursulin authored Nov 13, 2014
  6e7cc470
- drm/i915: Clear PCODE_DATA1 on SNB+ · dddab346
  Damien Lespiau authored Nov 13, 2014
  dddab346
- drm/i915/skl: Add Gen9 LRC size · 468c6816
  Michael H. Nguyen authored Nov 13, 2014
  468c6816
- drm/i915/skl: AUX irqs have moved · 88e04703
  Jesse Barnes authored Nov 13, 2014
  88e04703
- drm/i915/skl: fetch, enable/disable pfit as needed v2 · bd2e244f
  Jesse Barnes authored Nov 13, 2014
  bd2e244f
- drm/i915/skl: Implement queue_flip · 830c81db
  Damien Lespiau authored Nov 13, 2014
  830c81db
- drm/i915/skl: Apply eDP WA only for gen < 9 · 23f08d83
  Vandana Kannan authored Nov 13, 2014
  23f08d83
- drm/i915/skl: Provide skl-specific pll hw state cross-checking · 3f4cd19f
  Damien Lespiau authored Nov 13, 2014
  3f4cd19f
- drm/i915/skl: Implementation of SKL DPLL programming · 82d35437
  Satheeshakrishna M authored Nov 13, 2014
  82d35437
- drm/i915/skl: Adjust the port PLL selection code · efa80add
  Satheeshakrishna M authored Nov 13, 2014
  efa80add
- drm/i915/skl: Define shared DPLLs for Skylake · d1a2dc78
  Satheeshakrishna M authored Nov 13, 2014
  d1a2dc78
- drm/i915/skl: Query DPLL attached to port on SKL · 96b7dfb7
  Satheeshakrishna M authored Nov 13, 2014
  96b7dfb7
- drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock · 540e732c
  Satheeshakrishna M authored Nov 13, 2014
  540e732c
- drm/i915/skl: CD clock back calculation for SKL · 121643c2
  Satheeshakrishna M authored Nov 13, 2014
  121643c2
- drm/i915/skl: Structure/enum definitions for SKL clocks · 429d47d5
  Satheeshakrishna M authored Nov 13, 2014
  429d47d5
- drm/i915/skl: Register definitions for SKL Clocks · 326ac39b
  Satheeshakrishna M authored Nov 13, 2014
  326ac39b
- drm/i915: preserve SSC if previously set v3 · 92122789
  Jesse Barnes authored Oct 09, 2014
  92122789