Commits · 783d08bd02f5d33d6e9e7fea62b727e2b6fe6462 · jan.koester / Linux · GitLab

Jul 02, 2021
- Revert "clk: divider: Switch from .round_rate to .determine_rate by default" · 783d08bd
  Stephen Boyd authored Jul 01, 2021
  783d08bd
Jun 30, 2021
- clk: hisilicon: hi3559a: Drop __init markings everywhere · 498cc50b
  Stephen Boyd authored Jun 30, 2021
  498cc50b
- clk: meson: regmap: switch to determine_rate for the dividers · e4c5ef6b
  Martin Blumenstingl authored Jun 28, 2021
  e4c5ef6b
- clk: divider: Switch from .round_rate to .determine_rate by default · db400ac1
  Martin Blumenstingl authored Jun 28, 2021
  db400ac1
- clk: divider: Add re-usable determine_rate implementations · bbd7a6cc
  Martin Blumenstingl authored Jun 28, 2021
  bbd7a6cc
- clk: k210: Fix k210_clk_set_parent() · faa0e307
  Damien Le Moal authored Jun 22, 2021
  faa0e307
- clk: lmk04832: Fix spelling mistakes in dev_err messages and comments · 2cdee50e
  Colin Ian King authored Jun 29, 2021
  2cdee50e
- clk: lmk04832: fix return value check in lmk04832_probe() · b424f73b
  Wang Hai authored Jun 30, 2021
  b424f73b
- clk: stm32mp1: fix missing spin_lock_init() · b1f24771
  Wang Hai authored Jun 30, 2021
  b1f24771
Jun 29, 2021
- Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-next · d2b21013
  Stephen Boyd authored Jun 29, 2021
  d2b21013
- Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-ingenic' into clk-next · 4f47c91f
  Stephen Boyd authored Jun 29, 2021
  4f47c91f
- Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and... · e51fbc55
  Stephen Boyd authored Jun 29, 2021
  e51fbc55
- Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'clk-imx' into clk-next · 029eae23
  Stephen Boyd authored Jun 29, 2021
  029eae23
- Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and 'clk-ti' into clk-next · d915611e
  Stephen Boyd authored Jun 29, 2021
  d915611e
- clk: zynqmp: Handle divider specific read only flag · 03aea91b
  Rajan Vaja authored Jun 28, 2021
  03aea91b
- clk: zynqmp: Use firmware specific mux clock flags · 54530ed1
  Rajan Vaja authored Jun 28, 2021
  54530ed1
- clk: zynqmp: Use firmware specific divider clock flags · 1b09c308
  Rajan Vaja authored Jun 28, 2021
  1b09c308
- clk: zynqmp: Use firmware specific common clock flags · 610a5d83
  Rajan Vaja authored Jun 28, 2021
  610a5d83
- clk: lmk04832: Use of match table · bf68fdfd
  Stephen Boyd authored Jun 28, 2021
  bf68fdfd
- clk: lmk04832: Depend on SPI · 97a1c5cb
  Stephen Boyd authored Jun 28, 2021
  97a1c5cb
Jun 28, 2021
- clk: stm32mp1: new compatible for secure RCC support · 21e74330
  Gabriel Fernandez authored Jun 17, 2021
  21e74330
- dt-bindings: clock: stm32mp1 new compatible for secure rcc · 94b7888b
  Gabriel Fernandez authored Jun 17, 2021
  94b7888b
- dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 · f040e135
  Gabriel Fernandez authored Jun 17, 2021
  f040e135
- dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 · 256c7521
  Gabriel Fernandez authored Jun 17, 2021
  256c7521
- dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 · bd08b193
  Gabriel Fernandez authored Jun 17, 2021
  bd08b193
- reset: stm32mp1: remove stm32mp1 reset · 590ff40e
  Gabriel Fernandez authored Jun 17, 2021
  590ff40e
- clk: hisilicon: Add clock driver for hi3559A SoC · 6c819661
  Dongjiu Geng authored Mar 23, 2021
  6c819661
- dt-bindings: Document the hi3559a clock bindings · b87111da
  Dongjiu Geng authored Mar 23, 2021
  b87111da
- clk: si5341: Add sysfs properties to allow checking/resetting device faults · 9b13ff43
  Robert Hancock authored Mar 25, 2021
  9b13ff43
- clk: si5341: Add silabs,iovdd-33 property · 2f02c5e4
  Robert Hancock authored Mar 25, 2021
  2f02c5e4
- clk: si5341: Add silabs,xaxb-ext-clk property · ab89a343
  Robert Hancock authored Mar 25, 2021
  ab89a343
- clk: si5341: Allow different output VDD_SEL values · b7bbf6ec
  Robert Hancock authored Mar 25, 2021
  b7bbf6ec
- clk: si5341: Update initialization magic · 3c9b49b0
  Robert Hancock authored Mar 25, 2021
  3c9b49b0
- clk: si5341: Check for input clock presence and PLL lock on startup · 71dcc4d1
  Robert Hancock authored Mar 25, 2021
  71dcc4d1
- clk: si5341: Avoid divide errors due to bogus register contents · 78f6f406
  Robert Hancock authored Mar 25, 2021
  78f6f406
- clk: si5341: Wait for DEVICE_READY on startup · 6e7d2de1
  Robert Hancock authored Mar 25, 2021
  6e7d2de1
- dt-bindings: clock: clk-si5341: Add new attributes · c832bb98
  Robert Hancock authored Mar 25, 2021
  c832bb98
- drivers: ti: remove redundant error message in adpll.c · 9ba98c08
  Yu Jiahua authored Jun 15, 2021
  9ba98c08
- dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible · 301035c3
  Alain Volmat authored Mar 31, 2021
  301035c3
- clk: st: clkgen-fsyn: embed soc clock outputs within compatible data · 5dc1a127
  Alain Volmat authored Mar 31, 2021
  5dc1a127