Commits · a8f327fb8464875e5b764008a1c50dbc0b384c17 · jan.koester / Linux · GitLab

Sep 01, 2015
- drm/i915: Clean up CHV lane soft reset programming · a8f327fb
  Ville Syrjälä authored Jul 09, 2015
  a8f327fb
- drm/i915: Bump command parser version number. · 2bbe6bbb
  Francisco Jerez authored Jun 15, 2015
  2bbe6bbb
- drm/i915/dp: use the drm dp helper for determining sink tps3 support · caa860d9
  Jani Nikula authored Aug 27, 2015
  caa860d9
- drm/dp: add drm_dp_tps3_supported helper · 7cc53cf0
  Jani Nikula authored Aug 26, 2015
  7cc53cf0
Aug 28, 2015
- drm/i915: Update DRIVER_DATE to 20150828 · 01302d4d
  Daniel Vetter authored Aug 28, 2015
  01302d4d
Aug 26, 2015
- Partially revert "drm/i915: Use full atomic modeset." · c5b852f3
  Maarten Lankhorst authored Aug 26, 2015
  c5b852f3
- drm/i915: gen 9 can check for unclaimed registers too · 6c908bf4
  Paulo Zanoni authored Aug 25, 2015
  6c908bf4
- drm/i915: Force CL2 off in CHV x1 PHY · 3e288786
  Ville Syrjälä authored Jul 08, 2015
  3e288786
- drm/i915: Enable DPIO SUS clock gating on CHV · ee279218
  Ville Syrjälä authored Jul 08, 2015
  ee279218
- drm/i915: Force common lane on for the PPS kick on CHV · 0047eedc
  Ville Syrjälä authored Jul 10, 2015
  0047eedc
- drm/i915: Trick CL2 into life on CHV when using pipe B with port B · b0b33846
  Ville Syrjälä authored Jul 08, 2015
  b0b33846
- drm/i915: Implement PHY lane power gating for CHV · e0fce78f
  Ville Syrjälä authored Jul 08, 2015
  e0fce78f
- drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable · 5a8fbb7d
  Ville Syrjälä authored Jun 29, 2015
  5a8fbb7d
- drm/i915: Make some string arrays const · 4d9194de
  Ville Syrjälä authored Aug 21, 2015
  4d9194de
- drm/i915: Use ARRAY_SIZE() instead of hand rolling it · 53abb679
  Ville Syrjälä authored Aug 21, 2015
  53abb679
- drm/i915: Fix some gcc warnings · 0a0b457f
  Ville Syrjälä authored Aug 21, 2015
  0a0b457f
- drm/i915/bxt: Use correct live status register for BXT platform · e464bfde
  Jani Nikula authored Aug 20, 2015
  e464bfde
- drm/i915: split g4x_digital_port_connected to g4x and vlv variants · 9642c81c
  Jani Nikula authored Aug 20, 2015
  9642c81c
- drm/i915: split ibx_digital_port_connected to ibx and cpt variants · 0df53b77
  Jani Nikula authored Aug 20, 2015
  0df53b77
- drm/i915: add common intel_digital_port_connected function · 7e66bcf2
  Jani Nikula authored Aug 20, 2015
  7e66bcf2
- drm/i915: add MISSING_CASE annotation to ibx_digital_port_connected · 196cabd4
  Jani Nikula authored Aug 20, 2015
  196cabd4
- drm/i915: make g4x_digital_port_connected return boolean status · 1d245987
  Jani Nikula authored Aug 20, 2015
  1d245987
- drm/i915: move ibx_digital_port_connected to intel_dp.c · b93433cc
  Jani Nikula authored Aug 20, 2015
  b93433cc
- drm/i915: DVO pixel clock check · 26a91555
  Mika Kahola authored Aug 18, 2015
  26a91555
- drm/i915: DSI pixel clock check · 759a1e98
  Mika Kahola authored Aug 18, 2015
  759a1e98
- drm/i915: LVDS pixel clock check · 7f7b58cc
  Mika Kahola authored Aug 18, 2015
  7f7b58cc
- drm/i915: Store max dotclock · adafdc6f
  Mika Kahola authored Aug 18, 2015
  adafdc6f
- drm/i915: Add vlv_dport_to_phy() · 65d64cc5
  Ville Syrjälä authored Jul 08, 2015
  65d64cc5
- drm/i915: Move VLV/CHV prepare_pll later · c0b4c660
  Ville Syrjälä authored Jul 08, 2015
  c0b4c660
- drm/i915: Add locking around chv_phy_control_init() · 770effb1
  Ville Syrjälä authored Jul 08, 2015
  770effb1
- drm/i915: Move DPIO port init earlier · e27f299e
  Ville Syrjälä authored Jul 08, 2015
  e27f299e
- drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there · d6db995f
  Ville Syrjälä authored Jul 08, 2015
  d6db995f
- drm/i915: Always program unique transition scale for CHV · 67fa24b4
  Ville Syrjälä authored Jul 08, 2015
  67fa24b4
- drm/i915: Always program m2 fractional value on CHV · 25a25dfc
  Ville Syrjälä authored Jul 08, 2015
  25a25dfc
- drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCE · 4eee4920
  Dave Gordon authored Aug 17, 2015
  4eee4920
- drm/i915: Put back lane_count into intel_dp and add link_rate too · 901c2daf
  Ville Syrjälä authored Aug 17, 2015
  901c2daf
- drm/i915/bxt: don't allow cached GEM mappings on A stepping · e5756c10
  Imre Deak authored Aug 14, 2015
  e5756c10
- drm/i915/bxt: work around HW coherency issue when accessing GPU seqno · 319404df
  Imre Deak authored Aug 14, 2015
  319404df
- drm/i915: Also call frontbuffer flip when disabling planes. · 8be6ca85
  Rodrigo Vivi authored Aug 24, 2015
  8be6ca85
- drm/i915: Change SRM, LRM instructions to use correct length · f1afe24f
  Arun Siluvery authored Aug 04, 2015
  f1afe24f