Commits · b53a1603b46c5ee9b2fd4b276b12b916b33dc3d7 · jan.koester / Linux · GitLab

Dec 21, 2020
- Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next · b53a1603
  Stephen Boyd authored Dec 20, 2020
  b53a1603
- Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-summary' into clk-next · 699eda28
  Stephen Boyd authored Dec 20, 2020
  699eda28
- Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and... · d240d4c2
  Stephen Boyd authored Dec 20, 2020
  d240d4c2
- Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas'... · 23cae54f
  Stephen Boyd authored Dec 20, 2020
  23cae54f
Dec 19, 2020
- clk: si5351: Wait for bit clear after PLL reset · 5142cbce
  Sascha Hauer authored Nov 30, 2020
  5142cbce
- clk: at91: sam9x60: remove atmel,osc-bypass support · 01324f9e
  Alexandre Belloni authored Dec 02, 2020
  01324f9e
- clk: at91: sama7g5: register cpu clock · 91f3bf0d
  Claudiu Beznea authored Nov 19, 2020
  91f3bf0d
- clk: at91: clk-master: re-factor master clock · 7a110b91
  Claudiu Beznea authored Nov 19, 2020
  7a110b91
- clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz · 120d5d8b
  Claudiu Beznea authored Nov 19, 2020
  120d5d8b
- clk: at91: sama7g5: decrease lower limit for MCK0 rate · f803858a
  Claudiu Beznea authored Nov 19, 2020
  f803858a
- clk: at91: sama7g5: remove mck0 from parent list of other clocks · 4011f03e
  Claudiu Beznea authored Nov 19, 2020
  4011f03e
- clk: at91: clk-sam9x60-pll: allow runtime changes for pll · 8dc4af8b
  Claudiu Beznea authored Nov 19, 2020
  8dc4af8b
- clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics · 0bb4623f
  Eugen Hristev authored Nov 19, 2020
  0bb4623f
- clk: at91: clk-master: add 5th divisor for mck master · e26b3006
  Eugen Hristev authored Nov 19, 2020
  e26b3006
- clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT · 83d00287
  Eugen Hristev authored Nov 19, 2020
  83d00287
- dt-bindings: clock: at91: add sama7g5 pll defines · 3d86ee17
  Eugen Hristev authored Nov 19, 2020
  3d86ee17
- clk: at91: sama7g5: fix compilation error · 91274497
  Claudiu Beznea authored Nov 19, 2020
  91274497
Dec 17, 2020
- clk: Trace clk_set_rate() "range" functions · 03813d9b
  Maxime Ripard authored Dec 07, 2020
  03813d9b
- clk: axi-clkgen: move the OF table at the bottom of the file · 16214f97
  Alexandru Ardelean authored Dec 03, 2020
  16214f97
- clk: axi-clkgen: wrap limits in a struct and keep copy on the state object · ac1ee86a
  Alexandru Ardelean authored Dec 03, 2020
  ac1ee86a
- dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format · bd91abb2
  Alexandru Ardelean authored Oct 13, 2020
  bd91abb2
- clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs · 66cc7af3
  David Shah authored Dec 06, 2020
  66cc7af3
- clk: ti: Fix memleak in ti_fapll_synth_setup · 8c6239f6
  Zhang Qilong authored Nov 13, 2020
  8c6239f6
- clk: Add hardware-enable column to clk summary · bf6d43d7
  Dmitry Osipenko authored Nov 15, 2020
  bf6d43d7
- clk: mediatek: Make mtk_clk_register_mux() a static function · 2aeff9d8
  Weiyi Lu authored Nov 13, 2020
  2aeff9d8
Dec 16, 2020
- clk: sifive: Add clock enable and disable ops · 732374a0
  Pragnesh Patel authored Dec 09, 2020
  732374a0
- clk: sifive: Fix the wrong bit field shift · 263ac390
  Zong Li authored Dec 09, 2020
  263ac390
- clk: sifive: Add a driver for the SiFive FU740 PRCI IP block · efc91ae4
  Zong Li authored Dec 09, 2020
  efc91ae4
- clk: sifive: Use common name for prci configuration · 28108fc8
  Zong Li authored Dec 09, 2020
  28108fc8
- clk: sifive: Extract prci core to common base · c816e1dd
  Zong Li authored Dec 09, 2020
  c816e1dd
- dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI · a00a3f29
  Zong Li authored Nov 26, 2020
  a00a3f29
Dec 10, 2020
- Merge tag 'renesas-clk-for-v5.11-tag3' of... · fdc9b019
  Stephen Boyd authored Dec 10, 2020
  fdc9b019
- Merge tag 'clk-imx-5.11' of... · 958879d0
  Stephen Boyd authored Dec 10, 2020
  958879d0
- clk: tegra: Fix duplicated SE clock entry · 5bf5861d
  Dmitry Osipenko authored Oct 26, 2020
  5bf5861d
- clk: qcom: rpmh: add support for SM8350 rpmh clocks · f7b36cc1
  Vinod Koul authored Dec 08, 2020
  f7b36cc1
- dt-bindings: clock: Add RPMHCC bindings for SM8350 · eb50f3f4
  Vinod Koul authored Dec 08, 2020
  eb50f3f4
- clk: qcom: lpasscc: Introduce pm autosuspend for SC7180 · ce8c195e
  Taniya Das authored Nov 20, 2020
  ce8c195e
- clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2 · 04357751
  Douglas Anderson authored Dec 10, 2020
  04357751
- clk: qcom: gcc-sc7180: Use floor ops for sdcc clks · 6d37a8d1
  Douglas Anderson authored Dec 10, 2020
  6d37a8d1
- clk: scpi: mark scpi_clk_match as maybe unused · 975d25cb
  Krzysztof Kozlowski authored Nov 03, 2020
  975d25cb