Commits · cbd95a89996d1b5fadf411e9218c64e713a83099 · jan.koester / Linux · GitLab

Sep 03, 2015
- MIPS: mm: default platform_maar_init using bootmem data · cbd95a89
  Paul Burton authored Jul 10, 2015
  cbd95a89
- MIPS: MSA unaligned memory access support · e4aa1f15
  Leonid Yegoshin authored Jun 22, 2015
  e4aa1f15
- MIPS: Introduce accessors for MSA vector registers · 6b35e114
  Paul Burton authored Jun 22, 2015
  6b35e114
- MIPS: Declare MSA MI10 instruction formats · 6701ca2d
  Leonid Yegoshin authored Jun 22, 2015
  6701ca2d
- MIPS: Remove "__weak" definition from arch-specific linkage.h · b620c972
  Bjorn Helgaas authored Jul 12, 2015
  b620c972
- MIPS: Remove "weak" from mips_cdmm_phys_base() declaration · e1d97497
  Bjorn Helgaas authored Jul 12, 2015
  e1d97497
- MIPS: Remove "weak" from get_c0_fdc_int() declaration · 770847ba
  Bjorn Helgaas authored Jul 12, 2015
  770847ba
- MIPS: Remove "weak" from get_c0_compare_int() declaration · ec0b9d35
  Bjorn Helgaas authored Jul 12, 2015
  ec0b9d35
Aug 26, 2015
- MIPS: MT: Remove "weak" from vpe_run() declaration · c60f9944
  Bjorn Helgaas authored Jul 12, 2015
  c60f9944
- MIPS: VPE: Exit vpe_release() early if vpe_run() isn't defined · 1c205b9c
  Bjorn Helgaas authored Jul 12, 2015
  1c205b9c
- MIPS: Remove "weak" from platform_maar_init() declaration · 27d8d449
  Bjorn Helgaas authored Jul 12, 2015
  27d8d449
- MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it static · 8dedde6b
  Bjorn Helgaas authored Jul 12, 2015
  8dedde6b
- MIPS: Drop CONFIG_RUNTIME_DEBUG & debug.h · 9b4685de
  Paul Burton authored Jul 13, 2015
  9b4685de
- MIPS: ops-emma2rh: Drop nonsensical db_assert · 2dca88da
  Paul Burton authored Jul 13, 2015
  2dca88da
- MIPS: rt3883: Prepare rt3883_pci_irq_handler for irq argument removal · e51395d2
  Thomas Gleixner authored Jul 13, 2015
  e51395d2
- MIPS: netlogic: Prepare ipi handlers for irq argument removal · 31429d1a
  Thomas Gleixner authored Jul 13, 2015
  31429d1a
- MIPS: octeon: Replace the homebrewn flow handler · 56a86c35
  Thomas Gleixner authored Jul 13, 2015
  56a86c35
- MIPS: ath91: Remove pointless irqdisable/enable · 9d9a2fa7
  Thomas Gleixner authored Jul 13, 2015
  9d9a2fa7
- MIPS: alchemy: Remove pointless irqdisable/enable · e0288a0a
  Thomas Gleixner authored Jul 13, 2015
  e0288a0a
- MIPS: bcm63xx: Use irq_set_handler_locked() · 9154566e
  Thomas Gleixner authored Jul 13, 2015
  9154566e
- MIPS: alchemy: Use irq_set_chip_handler_name_locked() · 5a065450
  Thomas Gleixner authored Jul 13, 2015
  5a065450
- MIPS: irq: Use access helper irq_data_get_affinity_mask() · 5c159422
  Jiang Liu authored Jul 13, 2015
  5c159422
- MIPS: pci-rt3883: Consolidate chained IRQ handler install/remove · 586134a8
  Thomas Gleixner authored Jul 13, 2015
  586134a8
- MIPS: pci-ar724x: Consolidate chained IRQ handler install/remove · 4d3f77d8
  Thomas Gleixner authored Jul 13, 2015
  4d3f77d8
- MIPS: pci-ar71xx: Consolidate chained IRQ handler install/remove · 777fd18a
  Thomas Gleixner authored Jul 13, 2015
  777fd18a
- MIPS: jz4740: Consolidate chained IRQ handler install/remove · f058dc80
  Thomas Gleixner authored Jul 13, 2015
  f058dc80
- MIPS: Set up FTLB probability for I6400 · 20a7f7e5
  Markos Chandras authored Jul 09, 2015
  20a7f7e5
- MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6 · e87569cd
  Markos Chandras authored Jul 09, 2015
  e87569cd
- MIPS: Add default case for the FTLB enable/disable code · 912708c2
  Markos Chandras authored Jul 09, 2015
  912708c2
- MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB · c982c6d6
  Markos Chandras authored Jul 09, 2015
  c982c6d6
- IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs · 6f50c835
  Markos Chandras authored Jul 09, 2015
  6f50c835
- IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMs · c3f57f02
  Markos Chandras authored Jul 14, 2015
  c3f57f02
- MIPS: CM: Add support for reporting CM cache errors · 3885c2b4
  Markos Chandras authored Jul 09, 2015
  3885c2b4
- MIPS: CPC: Fix type for GCR CPC base reg for 64-bit · 391057d9
  Markos Chandras authored Jul 09, 2015
  391057d9
- MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels. · 038b0f53
  Markos Chandras authored Jul 09, 2015
  038b0f53
- MIPS: mips-cm: Extend CM accessors for 64-bit CPUs · c0b584a2
  Markos Chandras authored Jul 14, 2015
  c0b584a2
- MIPS: Add platform callback before initializing the L2 cache · c014d164
  Markos Chandras authored Jul 09, 2015
  c014d164
- MIPS: CM3: Add support for CM3 L2 cache. · 7d53e9c4
  Paul Burton authored Jul 09, 2015
  7d53e9c4
- MIPS: CM: Add GCR_L2_CONFIG register accessors · 0ba3c125
  Paul Burton authored Jul 09, 2015
  0ba3c125
- MIPS: mips-cm: Implement mips_cm_revision · 197e89e0
  Paul Burton authored Jul 10, 2015
  197e89e0