Commits · de43ae9dd263d50addd2c76b507dc0d1f1c5a1b3 · jan.koester / Linux · GitLab

Mar 17, 2015
- drm/i915/skl: Added new macros · de43ae9d
  Akash Goel authored Mar 06, 2015
  de43ae9d
- drm/i915: remove indirection in the PCI ID macros · 44e5e28b
  Jani Nikula authored Feb 03, 2015
  44e5e28b
- drm/i915: Use FW_WM() macro for older gmch platforms too · f4998963
  Ville Syrjälä authored Mar 10, 2015
  f4998963
- drm/i915: Add polish to VLV WM shift+mask operations · 15665979
  Ville Syrjälä authored Mar 10, 2015
  15665979
- drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore() · 6e721fb1
  Ville Syrjälä authored Mar 10, 2015
  6e721fb1
- drm/i915: Reduce clutter by using the local plane pointer · 3749f463
  Ville Syrjälä authored Mar 10, 2015
  3749f463
- drm/i915: Remove debug prints from primary plane update funcs · c5da5145
  Ville Syrjälä authored Mar 10, 2015
  c5da5145
- drm/i915: Add ULL postfix to VGT_MAGIC constant · 41659ab7
  Daniel Vetter authored Mar 11, 2015
  41659ab7
- drm/fourcc: 64 #defines need ULL postfix · 8c4f83fb
  Daniel Vetter authored Mar 11, 2015
  8c4f83fb
- drm/i915: Don't assume primary & cursor are always on for wm calculation (v4) · c9f038a1
  Matt Roper authored Mar 09, 2015
  c9f038a1
- drm/i915: Move drm_framebuffer_unreference out of struct_mutex for flips · 89ed88ba
  Chris Wilson authored Feb 16, 2015
  89ed88ba
- drm/i915: Disable DDR DVFS on CHV · fc1ac8de
  Ville Syrjälä authored Mar 05, 2015
  fc1ac8de
- drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV · cfb41411
  Ville Syrjälä authored Mar 05, 2015
  cfb41411
- drm/i915: Program PFI credits for VLV · 1e69cd74
  Vidya Srinivas authored Mar 05, 2015
  1e69cd74
- drm/i915: Rewrite VLV/CHV watermark code · ae80152d
  Ville Syrjälä authored Mar 05, 2015
  ae80152d
- drm/i915: Make sure we invalidate frontbuffer on fbcon. · 03e515f7
  Rodrigo Vivi authored Mar 09, 2015
  03e515f7
- drm/i915: Update prop, int co-eff and gain threshold for CHV · 9cbe40c1
  Vijay Purushothaman authored Mar 05, 2015
  9cbe40c1
- drm/i915: Initialize CHV digital lock detect threshold · de3a0fde
  Vijay Purushothaman authored Mar 05, 2015
  de3a0fde
- drm/i915: Disable M2 frac division for integer case · a945ce7e
  Vijay Purushothaman authored Mar 05, 2015
  a945ce7e
- drm/i915: Spelling s/auxilliary/auxiliary/ · ca2b1403
  Geert Uytterhoeven authored Mar 09, 2015
  ca2b1403
- drm/i915: Use crtc->state->active in ilk/skl watermark calculations (v3) · 3ef00284
  Matt Roper authored Mar 09, 2015
  3ef00284
- drm/i915: Update intel_crtc_active() to use state values (v2) · c3d1f436
  Matt Roper authored Mar 09, 2015
  c3d1f436
- drm/i915: Exit early from psr_status if PSR is not supported by the device · 3553a8ea
  Damien Lespiau authored Mar 09, 2015
  3553a8ea
- drm/i915: Fix chv cdclk support · 9d0d3fda
  Ville Syrjälä authored Mar 02, 2015
  9d0d3fda
- drm/i915: Allow pixel clock up to 95% of cdclk on CHV · 6cca3195
  Ville Syrjälä authored Mar 02, 2015
  6cca3195
- drm/i915/skl: port A fuse straps don't work on early SKL steppings · de31facd
  Jesse Barnes authored Mar 06, 2015
  de31facd
- drm/i915/skl: Restore the DDI translation tables when enabling PW1 · 1d2b9526
  Damien Lespiau authored Mar 06, 2015
  1d2b9526
- drm/i915: Remove unused condition in hsw_power_well_post_enable() · 25400392
  Damien Lespiau authored Mar 06, 2015
  25400392
- drm/i915/skl: Restore pipe interrupt registers after power well enabling · d14c0343
  Damien Lespiau authored Mar 06, 2015
  d14c0343
- drm/i915/skl: Mirror what we do on HSW for the power well enable log message · 510e6fdd
  Damien Lespiau authored Mar 06, 2015
  510e6fdd
- drm/i915/skl: Introduce enable_requested and is_enabled in the power well code · 2a51835f
  Damien Lespiau authored Mar 06, 2015
  2a51835f
- drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask · 4c6c03be
  Damien Lespiau authored Mar 06, 2015
  4c6c03be
- drm/i915/chv: Add CHV HW status to SSEU status · 5575f03a
  Jeff McGee authored Feb 27, 2015
  5575f03a
- drm/i915/chv: Determine CHV slice/subslice/EU info · c93043ae
  Jeff McGee authored Feb 27, 2015
  c93043ae
- drm/i915: Make sure PND deadline mode is enabled on VLV/CHV · c6beb13e
  Ville Syrjälä authored Mar 05, 2015
  c6beb13e
- drm/i915: Read out display FIFO size on VLV/CHV · b5004720
  Ville Syrjälä authored Mar 05, 2015
  b5004720
- drm/i915: Pass plane to vlv_compute_drain_latency() · 883a3d2f
  Ville Syrjälä authored Mar 05, 2015
  883a3d2f
- drm/i915: Reorganize VLV DDL setup · 0018fda1
  Ville Syrjälä authored Mar 05, 2015
  0018fda1
- drm/i915: Hide VLV DDL precision handling · 341c526f
  Ville Syrjälä authored Mar 05, 2015
  341c526f
- drm/i915: Simplify VLV drain latency computation · abfc00b5
  Ville Syrjälä authored Mar 05, 2015
  abfc00b5