Commits · debe6a623d3cdc7f0374124830587fb8d1a04b63 · jan.koester / Linux · GitLab

Feb 20, 2015
- MIPS: OCTEON: Update octeon-model.h code for new SoCs. · debe6a62
  David Daney authored Jan 15, 2015
  debe6a62
- MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX · e3d0ead5
  David Daney authored Jan 15, 2015
  e3d0ead5
- MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h · 664f1ae5
  David Daney authored Jan 15, 2015
  664f1ae5
- MIPS: OCTEON: Implement the core-16057 workaround · 664d699a
  David Daney authored Jan 15, 2015
  664d699a
- MIPS: OCTEON: Delete unused COP2 saving code · 69f7cd47
  Aleksey Makarov authored Jan 15, 2015
  69f7cd47
- MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register · 2d98cae6
  Chandrakala Chavva authored Jan 15, 2015
  2d98cae6
- MIPS: OCTEON: Save and restore CP2 SHA3 state · 6b3a287e
  David Daney authored Jan 15, 2015
  6b3a287e
- MIPS: OCTEON: Fix FP context save. · d6e41525
  David Daney authored Jan 15, 2015
  d6e41525
- MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs · ac655fb7
  David Daney authored Jan 15, 2015
  ac655fb7
- MIPS: boot: Provide more uImage options · 9d6b80fa
  Markos Chandras authored Feb 16, 2015
  9d6b80fa
- MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h · 151f9148
  David Daney authored Dec 18, 2014
  151f9148
- MIPS: ip22-gio: Remove legacy suspend/resume support · fa75da8e
  Lars-Peter Clausen authored Jan 11, 2015
  fa75da8e
- mips: pci: Add ifdef around pci_proc_domain · 6fb8a163
  Zubair Lutfullah Kakakhel authored Dec 12, 2014
  6fb8a163
- MIPS: Alchemy: Fix cpu clock calculation · 69e4e63e
  Manuel Lauss authored Feb 18, 2015
  69e4e63e
- MIPS: Alchemy: remove declaration for set_cpuspec · 200276e6
  Manuel Lauss authored Jan 29, 2015
  200276e6
- MIPS: Alchemy: preset loops_per_jiffy based on CPU clock · 45a848f7
  Manuel Lauss authored Jan 29, 2015
  45a848f7
- MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation · 51f105d3
  Manuel Lauss authored Jan 29, 2015
  51f105d3
- MIPS: Add set/clear CP0 macros for PageGrain register · a5770df0
  Steven J. Hill authored Feb 19, 2015
  a5770df0
Feb 19, 2015
- MIPS: Usage and cosmetic cleanups of page table bits. · 05f9883a
  Steven J. Hill authored Feb 19, 2015
  05f9883a
- Merge branch 'mipsr6-for-3.20' of... · 661af35e
  Ralf Baechle authored Feb 19, 2015
  661af35e
- MIPS: Export MSA functions used by lose_fpu(1) for KVM · ca5d2564
  James Hogan authored Feb 10, 2015
  ca5d2564
- MIPS: Export FP functions used by lose_fpu(1) for KVM · 3ce465e0
  James Hogan authored Feb 10, 2015
  3ce465e0
- MIPS: BCM3384: Fix outdated use of mips_cpu_intc_init() · 0e16d1e3
  Kevin Cernekee authored Dec 25, 2014
  0e16d1e3
- MIPS: Provide correct siginfo_t.si_stime · 8cb48fe1
  Petr Malat authored Dec 12, 2014
  8cb48fe1
- MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS · 32098ec7
  Markos Chandras authored Feb 02, 2015
  32098ec7
- MIPS: Makefile: Pass -march option on Loongson3A cores · a8140f36
  Ralf Baechle authored Feb 19, 2015
  a8140f36
Feb 17, 2015
- MIPS: Add Malta QEMU 32R6 defconfig · f296e7c4
  Markos Chandras authored Nov 24, 2014
  f296e7c4
- MIPS: Malta: Add support for building MIPS R6 kernel · 575509b6
  Markos Chandras authored Nov 19, 2014
  575509b6
- MIPS: kernel: elf: Improve the overall ABI and FPU mode checks · 46490b57
  Markos Chandras authored Jan 08, 2015
  46490b57
- MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6 · 6134d949
  Markos Chandras authored Jan 30, 2015
  6134d949
- MIPS: kernel: process: Do not allow FR=0 on MIPS R6 · 13e45f09
  Markos Chandras authored Jan 13, 2015
  13e45f09
- MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well · e0d32f33
  Markos Chandras authored Jan 15, 2015
  e0d32f33
- MIPS: Make use of the ERETNC instruction on MIPS R6 · 7c151d3d
  Markos Chandras authored Dec 03, 2014
  7c151d3d
- MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 · b0a668fb
  Leonid Yegoshin authored Dec 03, 2014
  b0a668fb
- MIPS: asm: mipsregs: Add support for the LLADDR register · b55b9e27
  Markos Chandras authored Dec 03, 2014
  b55b9e27
- MIPS: Add LLB bit and related feature for the Config 5 CP0 register · 5aed9da1
  Markos Chandras authored Dec 02, 2014
  5aed9da1
- MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions · 28d6f93d
  Markos Chandras authored Jan 08, 2015
  28d6f93d
- MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions · 69b9a2fd
  Markos Chandras authored Nov 27, 2014
  69b9a2fd
- MIPS: Emulate the new MIPS R6 BALC instruction · 84fef630
  Markos Chandras authored Nov 26, 2014
  84fef630
- MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions · 10d962d5
  Markos Chandras authored Nov 26, 2014
  10d962d5