Commits · ee249cbe42f19a7edac0e8cbb95064845e2e5218 · jan.koester / Linux · GitLab

Apr 12, 2017
- clk: zte: pd_bit is not 0 on zx296718 · ee249cbe
  Shawn Guo authored Mar 21, 2017
  ee249cbe
- clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks · 5790d801
  Shawn Guo authored Mar 21, 2017
  5790d801
- clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock · cf091ee9
  Robin van der Gracht authored Mar 03, 2017
  cf091ee9
- Merge tag 'tegra-for-4.12-clk' of... · 72be2d5f
  Michael Turquette authored Apr 12, 2017
  72be2d5f
- cs-2000-cp: keep Reserved bit on each register · 1f9dfd7a
  Kuninori Morimoto authored Apr 05, 2017
  1f9dfd7a
- clk: qcom: msm8996: Fix the vfe1 powerdomain name · a62ca337
  Rajendra Nayak authored Mar 23, 2017
  a62ca337
- clk: stm32f4: fix timeout management for pll and ready gate · ac03d8b3
  Gabriel Fernandez authored Mar 16, 2017
  ac03d8b3
- clk: iproc: Remove redundant check · d5a0945f
  Ray Jui authored Apr 05, 2017
  d5a0945f
- Merge tag 'v4.12-rockchip-clk1' of... · 55798360
  Michael Turquette authored Apr 12, 2017
  55798360
- Merge tag 'clk-renesas-for-v4.12-tag2' of... · 0d4ae360
  Michael Turquette authored Apr 12, 2017
  0d4ae360
- Merge branch 'clk-fixes' into clk-next · f37753e2
  Stephen Boyd authored Apr 04, 2017
  f37753e2
- clk: stm32f4: fix: exclude values 0 and 1 for PLLQ · ef189104
  Gabriel Fernandez authored Mar 16, 2017
  ef189104
- Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-next · 4641d6a5
  Stephen Boyd authored Apr 04, 2017
  4641d6a5
- clk: hi6220: add debug APB clock · b0459491
  Leo Yan authored Mar 26, 2017
  b0459491
Apr 04, 2017
- clk: tegra: Don't reset PLL-CX if it is already enabled · 1116d5a7
  Jon Hunter authored Mar 27, 2017
  1116d5a7
- clk: tegra: Add missing Tegra210 clocks · 88da44c5
  Peter De Schrijver authored Mar 22, 2017
  88da44c5
- clk: tegra: Propagate clk_out_x rate to parent · a63b6186
  Alex Frid authored Mar 22, 2017
  a63b6186
Mar 30, 2017
- clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 · bb195306
  Geert Uytterhoeven authored Mar 10, 2017
  bb195306
- clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 · 5573d194
  Geert Uytterhoeven authored Sep 29, 2016
  5573d194
- clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions · 89f1b1c6
  Geert Uytterhoeven authored Sep 29, 2016
  89f1b1c6
- clk: renesas: cpg-mssr: Add support for fixing up clock tables · 48d0341e
  Geert Uytterhoeven authored Sep 29, 2016
  48d0341e
Mar 23, 2017
- Merge tag 'sunxi-clk-fixes-for-4.11' of... · 7f0b97d5
  Stephen Boyd authored Mar 23, 2017
  7f0b97d5
Mar 22, 2017
- clk: rockchip: add pll_wait_lock for pll_enable · 9be83448
  Elaine Zhang authored Feb 22, 2017
  9be83448
- clk: rockchip: rename RK1108 to RV1108 · 7e2a9035
  Andy Yan authored Mar 17, 2017
  7e2a9035
- dt-bindings: rk1108-cru: rename RK1108 to RV1108 · b61753a4
  Andy Yan authored Mar 17, 2017
  b61753a4
Mar 21, 2017
- clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 · cecbe87d
  Geert Uytterhoeven authored Mar 10, 2017
  cecbe87d
- clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() · 5f3a432a
  Geert Uytterhoeven authored Mar 10, 2017
  5f3a432a
- clk: renesas: r8a7796: Reformat core clock table · c013fc7d
  Geert Uytterhoeven authored Nov 10, 2016
  c013fc7d
- clk: renesas: r8a7795: Reformat core clock table · 3c969cec
  Geert Uytterhoeven authored Nov 10, 2016
  3c969cec
- clk: renesas: r8a7796: Correct name of watchdog clock · 89aa58a3
  Geert Uytterhoeven authored Feb 28, 2017
  89aa58a3
- clk: renesas: r8a7795: Correct name of watchdog clock · 2122b56d
  Geert Uytterhoeven authored Feb 28, 2017
  2122b56d
- clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs · a843ed3f
  Geert Uytterhoeven authored Feb 28, 2017
  a843ed3f
Mar 20, 2017
- clk: tegra: Fix build warnings on Tegra20/Tegra30 · 39133505
  Thierry Reding authored Mar 20, 2017
  39133505
- clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on · bea1baa1
  Peter De Schrijver authored Feb 28, 2017
  bea1baa1
- clk: tegra: Add SATA seq input control · 59af78d7
  Peter De Schrijver authored Mar 15, 2017
  59af78d7
- clk: tegra: Add Tegra210 special resets · 68d724ce
  Peter De Schrijver authored Mar 15, 2017
  68d724ce
- clk: tegra: Rework pll_u · e745f992
  Peter De Schrijver authored Mar 14, 2017
  e745f992
- clk: tegra: Implement reset control reset · 4236e752
  Mikko Perttunen authored Mar 02, 2017
  4236e752
- clk: tegra: Fix disable unused for clocks sharing enable bit · 9619dba8
  Peter De Schrijver authored Mar 02, 2017
  9619dba8
- clk: tegra: Handle UTMIPLL IDDQ · 3843832f
  Peter De Schrijver authored Feb 28, 2017
  3843832f