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Commit b98ab70e authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
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drm/amd/display: Hardcode 45W Bounding Box for DCN2.1 Diags



[WHY]
Currently construction of clock limits gets skipped for diags.
This logic would be useful to get tested in diags.

[HOW]
Copy existing states to clk_table such that update_bw_bounding_box
logic gets used to fill the table.

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5dff371a
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