Commits · bd189aac5a91adf88eb5fac062c9d4a0c005c805 · jan.koester / Linux · GitLab

Dec 07, 2020
- media: ccs-pll: Print pixel rates · bd189aac
  Sakari Ailus authored Sep 23, 2020
  bd189aac
- media: ccs: Print written register values · ba9dfeeb
  Sakari Ailus authored Sep 22, 2020
  ba9dfeeb
- media: ccs: Add support for DDR OP SYS and OP PIX clocks · 7c66f58f
  Sakari Ailus authored Sep 23, 2020
  7c66f58f
- media: ccs-pll: Add support for DDR OP system and pixel clocks · 900c33e8
  Sakari Ailus authored Aug 25, 2020
  900c33e8
- media: ccs: Dual PLL support · b41f2708
  Sakari Ailus authored Sep 16, 2020
  b41f2708
- media: ccs-pll: Add trivial dual PLL support · 6c7469e4
  Sakari Ailus authored Sep 15, 2020
  6c7469e4
- media: ccs-pll: Separate VT divisor limit calculation from the rest · 9ec6e5b1
  Sakari Ailus authored Sep 15, 2020
  9ec6e5b1
- media: ccs-pll: Fix VT post-PLL divisor calculation · 36154b68
  Sakari Ailus authored Sep 15, 2020
  36154b68
- media: ccs-pll: Make VT divisors 16-bit · 594f1e93
  Sakari Ailus authored Sep 15, 2020
  594f1e93
- media: ccs-pll: Rework bounds checks · f25d3962
  Sakari Ailus authored Sep 15, 2020
  f25d3962
- media: ccs-pll: Print relevant information on PLL tree · fadfe884
  Sakari Ailus authored Sep 09, 2020
  fadfe884
- media: ccs-pll: Better separate OP and VT sub-tree calculation · a38836b2
  Sakari Ailus authored Sep 04, 2020
  a38836b2
- media: ccs-pll: Check for derating and overrating, support non-derating sensors · 38c94eb8
  Sakari Ailus authored Aug 28, 2020
  38c94eb8
- media: ccs-pll: Split off VT subtree calculation · 3e2db036
  Sakari Ailus authored Aug 25, 2020
  3e2db036
- media: ccs-pll: Add C-PHY support · 8030aa4f
  Sakari Ailus authored Jul 03, 2020
  8030aa4f
- media: ccs-pll: Add sanity checks · d7172c0e
  Sakari Ailus authored Aug 04, 2020
  d7172c0e
- media: ccs-pll: Add support flexible OP PLL pixel clock divider · 9490a227
  Sakari Ailus authored Aug 07, 2020
  9490a227
- media: ccs-pll: Support two cycles per pixel on OP domain · c4c0b222
  Sakari Ailus authored Aug 07, 2020
  c4c0b222
- media: ccs-pll: Add support for extended input PLL clock divider · 4e1e8d24
  Sakari Ailus authored Jun 23, 2020
  4e1e8d24
- media: ccs-pll: Add support for decoupled OP domain calculation · ae502e08
  Sakari Ailus authored Jun 18, 2020
  ae502e08
- media: ccs: Add support for lane speed model · 585e17c9
  Sakari Ailus authored Sep 23, 2020
  585e17c9
- media: ccs-pll: Add support for lane speed model · cac8f5d2
  Sakari Ailus authored Jun 22, 2020
  cac8f5d2
- media: ccs-pll: Use explicit 32-bit unsigned type · e583e654
  Sakari Ailus authored Aug 25, 2020
  e583e654
- media: ccs-pll: Fix check for PLL multiplier upper bound · 82ab97c8
  Sakari Ailus authored Jul 07, 2020
  82ab97c8
- media: ccs-pll: Fix comment on check against maximum PLL multiplier · c64cf71d
  Sakari Ailus authored Jul 07, 2020
  c64cf71d
- media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search · 482e75e7
  Sakari Ailus authored Jul 07, 2020
  482e75e7
- media: ccs-pll: Fix condition for pre-PLL divider lower bound · fe52ece8
  Sakari Ailus authored Jul 07, 2020
  fe52ece8
- media: ccs-pll: Begin calculation from OP system clock frequency · cab27256
  Sakari Ailus authored Jun 26, 2020
  cab27256
- media: ccs-pll: Use the BIT macro · 4f3d9e6e
  Sakari Ailus authored Jun 17, 2020
  4f3d9e6e
- media: ccs-pll: Document the structs in the header as well as the function · 925e3e49
  Sakari Ailus authored Jun 08, 2020
  925e3e49
- media: ccs-pll: Move the flags field down, away from 8-bit fields · d6a88e44
  Sakari Ailus authored Jun 23, 2020
  d6a88e44
- media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY · 47b6eaf3
  Sakari Ailus authored Jun 22, 2020
  47b6eaf3
- media: ccs-pll: Remove parallel bus support · 6aadbff9
  Sakari Ailus authored Jun 18, 2020
  6aadbff9
- media: ccs-pll: End search if there are no better values available · 9c1a0d9e
  Sakari Ailus authored Sep 01, 2020
  9c1a0d9e
- media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor · 9454432a
  Sakari Ailus authored Sep 01, 2020
  9454432a
- media: ccs-pll: Split limits and PLL configuration into front and back parts · 415ddd99
  Sakari Ailus authored Jun 05, 2020
  415ddd99
- media: ccs-pll: Don't use div_u64 to divide a 32-bit number · c3833a22
  Sakari Ailus authored Jun 25, 2020
  c3833a22
- media: dt-bindings: schema indentation fixes · 58379119
  Rob Herring authored Nov 12, 2020
  58379119
- media: vivid: fix 'disconnect' error injection · 9e5f21d6
  Hans Verkuil authored Dec 01, 2020
  9e5f21d6
- media: rcar-vin: Mask VNCSI_IFMD register · fb25ca37
  Jacopo Mondi authored Nov 26, 2020
  fb25ca37